Characterization Methods for BTI Degradation and Associated Gate Insulator Defects

Mahapatra, S.; Goel, Nilesh; Chaudhary, Ankush; Joshi, K.; Mukhopadhyay, Subhadeep

doi:10.1007/978-81-322-2508-9_2

Cited by 18 publications

(4 citation statements)

References 56 publications

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“…The NBTI can also be explained through the stress oxide electric field at the Si-SiO2 interface (Eox), which is expressed by equation (1) for NW [5] and equation 2for planar device [13]:…”

Section: Resultsmentioning

confidence: 99%

Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

Silva

Wirth²,

Martino³

et al. 2020

JICS

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This work presents an experimental andThis work presents an experimental and simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation. simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation.

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“…The NBTI can also be explained through the stress oxide electric field at the Si-SiO2 interface (Eox), which is expressed by equation (1) for NW [5] and equation 2for planar device [13]:…”

Section: Resultsmentioning

confidence: 99%

Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

Silva

Wirth²,

Martino³

et al. 2020

JICS

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“…The device transfer curve are evaluated before and after BTI stress for determining the variation in the parameters. This technique is called as the measure‐stress‐measure (MSM) 22–25 . In this technique, initially the I–V characteristics of the fresh device is measured, then the stress is applied at high temperature for some time interval, for example, 2000s.…”

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

“…This technique is called as the measure-stress-measure (MSM). [22][23][24][25] In this technique, initially the I-V characteristics of the fresh device is measured, then the stress is applied at high temperature for some time interval, for example, 2000s. This process is repeated several times to measure the degradation due to BTI stress.…”

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Kumar,

Panchore

2024

Int J Numerical Modelling

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In this paper, an assessment of bias temperature instability (BTI) in based dual gate dopingless JLFET (HKV‐DLJLFET) is carried out at 15 nm technology node. For this, the gate dielectric of HKV‐DGDLJLFET is made of asymmetric combination of and vacuum dielectrics near the source/drain (S/D) side, which significantly minimizes the leakage current and enhances the reliability. Our simulation study have shown that the n‐type HKV‐DGDLJLFET exhibits 2.28 and 2.45 times less deterioration in drain current and transconductance respectively, than n‐type HKV‐DGJLFET due to positive BTI (PBTI) for 2000 seconds at . Further, we have found that n‐type HKV‐DGDLJLFET has less deterioration in and due to BTI stress for different time spans. Hence, adding vacuum dielectric to the drain side lowers the BTI stress at high temperatures and makes it last longer.

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“…Keysight B1530 enabled with Waveform Generator/ Fast Measuring Unit (WGFMU) is used for ultrafast electrical characterization. The Measure-Stress-Measure (MSM) scheme is used to measure the drain current drift in a logarithmic time interval and later translated to threshold voltage shift using the lateral shift method [29]. The measurement delay is kept close to ~10us to reduce the impact of the recovery-related artefacts.…”

Section: Device Details and Measurement Descriptionmentioning

confidence: 99%

Modeling of DC - AC NBTI Stress - Recovery Time Kinetics in P-Channel Planar Bulk and FDSOI MOSFETs and FinFETs

Choudhury

Parihar

Goel

et al. 2020

IEEE J. Electron Devices Soc.

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The physics-based BTI Analysis Tool (BAT) is used to model the time kinetics of threshold voltage shift (VT) during and after NBTI in p-channel planar bulk and FDSOI MOSFETs and SOI FinFETs. BAT uses uncorrelated contributions from the trap generation at the channel/gate insulator interface (VIT) and gate insulator bulk (VOT), and hole trapping in pre-existing gate insulator bulk traps (VHT). The VIT kinetics is simulated by the Reaction-Diffusion (RD) model. The empirical VHT model used earlier is now substituted by the Activated Barrier Double Well Thermionic (ABDWT) model. The ABDWT model is also used to verify the time constant of the electron capture induced fast VIT recovery. Empirical equations are used for VOT. The enhanced BAT modeling framework is validated using measured data from a wide range of experimental conditions and across different device architectures and gate insulator processes.

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Characterization Methods for BTI Degradation and Associated Gate Insulator Defects

Cited by 18 publications

References 56 publications

Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Modeling of DC - AC NBTI Stress - Recovery Time Kinetics in P-Channel Planar Bulk and FDSOI MOSFETs and FinFETs

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