Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias

Saadat, Hassaan; Javaid, Haris; Parameswaran, Sri

doi:10.1145/3316781.3317773

Cited by 34 publications

(24 citation statements)

References 20 publications

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“…We have evaluated SIMDive against five SIMD and SISD accurate and approximate cutting-edge multipliers and dividers: performance-optimized accurate IPs of multiplier [36] and divider [37], provided by Xilinx Vivado, Mitchell [22], SoAs MBM [28], INZeD [29] and AAXD dividers [29] as they have the best resource-error trade-off when compared to the rest of designs ( [9,13,20,33]), CA [30] (based on approximate 4x4 multipliers) customized for FPGAs, and truncated multiplier (with 7x7 or 15x7 as the basic multiplier, the more accurate one is also exploited in SIMD structure). Note, hierarchical SIMD divider is not mathematically feasible by decomposing large one to small instances.…”

Section: Results and Discussion 41 Experimental Setupmentioning

confidence: 99%

“…• Finally, Fig.1 (c) shows diverse distribution of relative error. This means employing a single error-coefficient to the whole interval (as proposed in SoA MBM [28] and INZeD [29]), is not efficient and results in many output overflow cases. Coalescing the insights from above points incentivize using multiple error-reduction terms appropriately opted based on summation of fractional parts to cope with overflow and yet enduring minimal latency overhead.…”

Section: Proposed Light-weight Error-reduction Schemementioning

confidence: 99%

“…Most of the architectures in the literature, approximate fixed word-length multipliers or dividers, or SIMD multipliers [8,23,28,29]. These techniques are not generic since approximation principles (as defined for ASIC) neglect differences in the underlying reconfigurable infrastructure and yield insignificant improvements when directly synthesized and ported to FPGAs [31].…”

Section: Introductionmentioning

confidence: 99%

“…Our error-coefficients are added with the same LUTs and their associated fast carry chains, already used for the addition step of Mitchell's algorithm. This addresses the prolonged critical path in cutting-edge approaches [21,28,29]. We are also able to increase accuracy by one-bit and limit error to a desirable bound using one more LUT (99.2% accuracy with eight LUTs).…”

Section: Introductionmentioning

confidence: 99%

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SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy

Ebrahimi

Ullah

Kumar

2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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The ever-increasing quest for data-level parallelism and variable precision in ubiquitous multimedia and Deep Neural Network (DNN) applications has motivated the use of Single Instruction, Multiple Data (SIMD) architectures. To alleviate energy as their main resource constraint, approximate computing has re-emerged, albeit mainly specialized for their Application-Specific Integrated Circuit (ASIC) implementations. This paper, presents for the first time, an SIMD architecture based on novel multiplier and divider with tunable accuracy, targeted for Field-Programmable Gate Arrays (FPGAs). The proposed hybrid architecture implements Mitchell's algorithms and supports precision variability from 8 to 32 bits. Experimental results obtained from Vivado, multimedia and DNN applications indicate superiority of proposed architecture (both SISD and SIMD) over accurate and state-of-the-art approximate counterparts. In particular, the proposed SISD divider outperforms the accurate Intellectual Property (IP) divider provided by Xilinx with 4× higher speed and 4.6×less energy and tolerating only <0.8% error. Moreover, the proposed SIMD multiplier-divider supersede accurate SIMD multiplier by achieving up to 26%, 45%, 36%, and 56% improvement in area, throughput, power, and energy, respectively.

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Section: Results and Discussion 41 Experimental Setupmentioning

confidence: 99%

Section: Proposed Light-weight Error-reduction Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy

Ebrahimi

Ullah

Kumar

2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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“…1 We survey synthesis strategies for automatically deriving approximate circuits from a description of their (exact) functionality and from a notion of the allowed degree of inexactness. The first works in circuit approximation were the result of manual design, i.e., approximate adders [65], [70], multipliers [10], [15], [22], [40] or dividers [16], [42] were created to design single inexact implementations of arithmetic units. Other works [20], [21] present algorithms that allow to automatically explore the energy-quality tradeoff, but again limit the analysis to adders and multipliers only.…”

Section: Introductionmentioning

confidence: 99%

Approximate Logic Synthesis: A Survey

et al. 2020

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Approximate computing is an emerging paradigm that, by relaxing the requirement for full accuracy, offers benefits in terms of design area and power consumption. This paradigm is particularly attractive in applications where the underlying computation has inherent resilience to small errors. Such applications are abundant in many domains, including machine learning, computer vision and signal processing. In circuit design, a major challenge is the capability to synthesize approximate circuits automatically, without manually relying on the expertise of designers. In this work, we review methods devised to synthesize approximate circuits given their exact functionality and an approximability threshold. We summarize strategies for evaluating the error that circuit simplification can induce on the output, which guide synthesis techniques in choosing the circuit transformations that lead to the largest benefit for a given amount of induced error. We then review circuit simplification methods that operate at gate or Boolean level, including those that leverage classical Boolean synthesis techniques to realize the approximations. We also summarize strategies that take highlevel descriptions such as C or behavioral Verilog and synthesize approximate circuits from these descriptions.

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