Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier

Gandhi, S. Girish; Ansari, Mohammad Saeed; Cockburn, B.F.; Han, Jie

doi:10.1109/ccece.2019.8861800

Cited by 15 publications

(8 citation statements)

References 6 publications

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“…The proposed design increases the accuracy of Mitchell's multiplier by 44.7%, on average, but almost doubles the number of logic gates. To reduce area and energy consumption of Mitchell multiplier, Gandhi et al [16] employed approximate leading-one detectors. With the employment of approximate leading-one detectors, authors lowered the energy consumption of Mitchell multiplier by 55 %.…”

Section: A Approximate Logarithmic Multipliersmentioning

confidence: 99%

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On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Pilipović

Bulić

2020

IEEE Access

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This paper proposes an energy-efficient approximate multiplier which combines radix-4 Booth encoding and logarithmic product approximation. Additionally, a datapath pruning technique is proposed and studied to reduce the hardware complexity of the multiplier. Various experiments were conducted to evaluate the multiplier's error performance and efficiency in terms of energy and area utilization. The reported results are based on simulations using TSMC-180nm. Also, the applicability of the proposed multiplier is examined in image sharpening and convolutional neural networks. The applicability assessment shows that the proposed multiplier can replace an exact multiplier and deliver up to a 75% reduction in energy consumption and up to a 50% reduction in area utilization. Comparative analysis with the state-of-the-art multipliers indicates the potential of the proposed approach as a novel design strategy for approximate multipliers. When compared to the state-of-the-art approximate non-logarithmic multipliers, the proposed multiplier offers smaller energy consumption with the same level of applicability in image processing and classification applications. On the other hand, some state-of-the-art approximate logarithmic multipliers exhibit lower energy consumption than the proposed multiplier but deliver significant performance degradation for the selected application cases. INDEX TERMS Approximate computing, arithmetic circuit design, booth encoding, logarithmic multipliers, multipliers, power-efficient processing, truncated multipliers.

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Section: A Approximate Logarithmic Multipliersmentioning

confidence: 99%

“…(5)) of the multiplicand, which is approximated in the LPPG stage, while the parameters T S and T H represent the pruning thresholds (Eq. (16) and Eq. 18).…”

Section: Error Characteristics Of the Lobo Multipliermentioning

confidence: 99%

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Pilipović

Bulić

2020

IEEE Access

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“…Since both designs generate accurate results for inputs greater than 2 16 , and considering that 2 16 is only 0.001% of the 32-bit input domain, almost all the error metrics were zero (no error), even for 10 9 randomly generated inputs. Hence, we limited the maximum input to 2 18 , 2 20 , and 2 22 and the results are provided in Table 3.…”

Section: Accuracy Analysismentioning

confidence: 99%

“…This significantly reduces the hardware complexity and speeds up the multiplication. Some of our preliminary work was published in [18]. In this article, the two approximate LOD designs in [18] are modified to improve their accuracy.…”

Section: Introductionmentioning

confidence: 99%

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Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing

Ansari

Gandhi

Cockburn

et al. 2021

IET Computers & Digital Tech

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The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading-one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to approximate the d least significant bits (LSBs) in the outputs of the LOD. The second design (LOD II) partitions the d LSBs into smaller fields and uses a multiplexer to select the closest approximation to the exact value. These two LODs help with error cancellation as they introduce signed errors for inputs N < 2 d . Additionally, a scaling scheme is proposed that scales up the input N < 2 d to avoid large approximation errors. Finally, an improved exact LOD (LOD III) is proposed that only passes half of the input N to the LOD; the more significant half is passed if there is at least one '1' in that half; otherwise, the less significant half is passed. Our simulation results show that the 32-bit LOD III can be up to 2.8� more energy-efficient than existing designs in the literature. The Mitchell logarithmic multiplier and a neural network are considered to further illustrate the practicality of the proposed designs.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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A low‐error, memory‐based fast binary antilogarithmic converter

Harsha

Jammu

Samoju

et al. 2021

Circuit Theory & Apps

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SummaryThe ever‐increasing need for high‐performance signal processing blocks in avionics, machine learning (ML), IoT, neural networks, etc., has made the logarithmic arithmetic's as the front runner in advanced processors. The complex arithmetic operations such as multiplication and division can be easily performed in the logarithmic domain as they become addition and subtraction operations, respectively. However, the challenge is to perform the logarithmic and anti‐logarithmic conversions and to optimize the trade‐off between hardware complexity and accuracy. In this work, we propose a 32‐bit antilogarithmic converter, for/using Mitchell's algorithm. The obtained results are corrected using the weighted average method. The correction terms are stored and selected using 32 × 8 ROM to decreases the computational speed and hardware complexity of the antilogarithmic converter. The proposed antilogarithmic converter has a maximum error percentage of 1.199%, which is 6.147% for Mitchell's algorithm while maintaining the hardware metrics close to Mitchell's algorithm.

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Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier

Cited by 15 publications

References 6 publications

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing

A low‐error, memory‐based fast binary antilogarithmic converter

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