Approximate Logic Synthesis by Symmetrization

Abstract

Approximate synthesis is a recent trend in logic synthesis that changes some outputs of a logic specification to take advantage of error tolerance of some applications and reduce complexity and consumption of the final implementation. We propose a new approach to approximate synthesis of combinational logic where we derive its closest symmetric approximation, i.e., the symmetric function obtained by injecting the minimum number of errors in the original function. Since BDDs of totally symmetric functions are quite compact, this approach is particularly convenient for BDD-based implementations, such as networks of MUXes directly mapped from BDDs. Our contribution is twofold: first we propose a polynomial algorithm for computing the closest symmetric approximation of an incompletely specified Boolean function with an unbounded number of errors; then we discuss strategies to achieve partial symmetrization of the original specification while satisfying given error bounds. Experimental results on classical and new benchmarks confirm the efficacy of the proposed approach.

Computing the full quotient in bi-decomposition by approximation

“…We are also interested in the investigation of bidecomposition combined with approximation methods that derive the closest approximate regular version of a given Boolean function, as proposed for instance in [3]. Indeed, the approximation toward regularity approach presents a drawback: it may introduce an unbounded number of errors, producing a low-quality approximation g. Our approach, however, can overcome this problem, thanks to the presence of the function h, whose aim is precisely to correct the errors introduced by the function g. Moreover, we could derive h, and then exploit it to correct partially instead than totally the errors introduced by g. In other words, we could use h to correct the unbounded 'regular' approximation g, and then approximate h, in any bounded-error approximation framework, in order to derive an overall compact approximation of the original function f , with a bounded number of errors.…”

Two-Level and Multilevel Approximate Logic Synthesis

“…They also present algorithms to estimate the inserted error by traversing the BDD. Moreover, once symmetric functions tend to result in a more compact BDD representation, Bernasconi et al,in [30,31], propose a way to transform a given function into a symmetrical or partially symmetric one.…”

“…ALS method Data structure Error metric [20,22] Boolean network ER, WCE [21] Boolean network WCE, WCRE [23][24][25] Boolean network ER, MAE [32,33] Boolean network ER [36] Boolean network BER [37,47] Boolean network ER, MRE [40,41] Boolean network WBF, MAE [42,49] Boolean network WCE [26] AIG WCE [38] AIG WCE, MSE [39,46] AIG ER [43] AIG WBF, ER, WCE [44] AIG ER, MAE [27,45] AIG ER, MAE, MRE [48] AIG ER, MAE, WCE [28] BDD ER, MAE, WCE [29] BDD ER, MAE, MRE [30,31] BDD BER [34] LUT ER [35] LUT BER, ER circuits in a sequential design, also presenting a particular error calculation technique for this scenario.…”

Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis

“…This paper is an extended version of the conference paper presented in [12] and is organized as follows. Previous work is reviewed in Sec.…”