Approximate-min* constraint node updating for ldpc code decoding

Jones, Christopher R.; Valles, Esteban L.; Smith, M.J.T.; Villasenor, John

doi:10.1109/milcom.2003.1290095

Cited by 61 publications

(31 citation statements)

References 9 publications

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“…First, let the parameters K and J (the constraint and variable node degrees) be denoted by K avg = 5 and J avg = 3. Second, assume that a degree K avg constraint node requires C check = 2K avg 2-input operations to perform an update; similarly a degree J avg variable node requires C var = 2J avg 2-input operations (see, for instance, [11]). Given these assumptions, we refer the reader to Table I. Without biasing results to one approach over the other, the results in the table assume that all variable nodes in the code are transmitted and must be buffered in the decoding process.…”

Section: Comparison Of Block and Convolutional Codes Built Frommentioning

confidence: 99%

A Comparison of ARA- and Protograph-Based LDPC Block and Convolutional Codes

Costello

Pusane

Jones

et al. 2007

2007 Information Theory and Applications Workshop

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Abstract-ARA-and protograph-based LDPC codes are capable of achieving error performance similar to randomly constructed codes while enjoying several implementation advantages as a result of their structure. LDPC convolutional codes can be derived from these codes through an unwrapping process. In this paper, we review the unwrapping process as well as the pipeline decoder that allows continuous decoding of LDPC convolutional codes. Computer simulations are then used to demonstrate that the unwrapped convolutional codes achieve a "convolutional gain" in error performance. We conjecture that this is due to the concatenation of many constraint lengths worth of received symbols in the pipeline decoding process. The consequences of this improved performance are examined in terms of factors related to decoder implementation: processor size, memory requirements, and decoding delay (latency). Finally, given identical protograph kernels, we compare derived block and convolutional codes based on the above measures.

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Section: Comparison Of Block and Convolutional Codes Built Frommentioning

confidence: 99%

A Comparison of ARA- and Protograph-Based LDPC Block and Convolutional Codes

Costello

Pusane

Jones

et al. 2007

2007 Information Theory and Applications Workshop

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“…From (1), the magnitude of L (i) e,j,l computed by the BP algorithm, however, is always less than that of the min-sum algorithm and equality holds only when all variable nodes are in B( j)/l, however the minimum values, have their LLR magnitude very large, ideally 1. On the other hand, when the LLRs of the variable nodes are small or the check weight r ¼ |B( j)| becomes large, l ′ [B(j)\l tanh(|L (i−1) j,l ′ |/2) becomes much smaller than min l ′ [B(j)\l {|L (i−1) j,l ′ |}, causing difference in calculation between the min-sum and BP algorithms [3,4] and hence performance loss.…”

Section: Introductionmentioning

confidence: 99%

“…Variants of the offset BP-based algorithm are proposed in [4,5,9], where attempts are made to endow the decoders with flexibility by adaptively changing the offset value to achieve good decoding without using density evolution. These decoders mostly use either piecewise constant or linear approximations [10] to represent the offset, which is a non-linear function of the intrinsic information, and are based on the Jacobian logarithm [11].…”

Section: Introductionmentioning

confidence: 99%

Different perspective and approach to implement adaptive normalised belief propagation-based decoding for low-density parity check codes

Poocharoen

Magaña

2012

IET Commun.

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In this study, the authors propose an improved version of the min-sum algorithm for low-density parity check code decoding, which the authors call 'adaptive normalised BP-based' algorithm. Their decoder provides a compromise solution between belief propagation and the min-sum algorithms by adding an exponent offset to each variable node's intrinsic information in the check node update equation. The extrinsic information from the min-sum decoder is then adjusted by applying a negative power of the two scale factor, which can be easily implemented by right shifting the min-sum extrinsic information. The difference between their approach and other adaptive normalised min-sum decoders is that the authors select the normalisation scale factor using a clear analytical approach based on the underlying principles. The simulation results show that the proposed decoder outperforms the min-sum decoder and performs very close to the BP decoder with lower complexity.

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“…Our implementation passes these tests even with extremely large numbers of samples. In addition, our noise generator has successfully been used in Low-density parity-check code decoding experiments [21]. Three instances of the noise generator are used for the BGM implementation, in order to generate three noise samples every cycle.…”

Section: A Linear Feedback Based Shift Register (Lfsr)mentioning

confidence: 99%

Reconfigurable acceleration for Monte Carlo based financial simulation

Zhang

Leong

et al.

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

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This paper describes a novel hardware accelerator for Monte Carlo (MC) simulation, and illustrates its implementation in field programmable gate array (FPGA) technology for speeding up financial applications. Our accelerator is based on a generic architecture, which combines speed and flexibility by integrating a pipelined MC core with an on-chip instruction processor. We develop a generic number system representation for determining the choice of number representation that meets numerical precision requirements. Our approach is then used in a complex financial engineering application, involving the Brace, Gatarek and Musiela (BGM) interest rate model for pricing derivatives. We address, in our BGM model, several challenges including the generation of Gaussian distributed random numbers and pipelining of the MC simulation. Our BGM application, based on an off-the-shelf system with a Xilinx XC2VP30 device at 50 MHz, is over 25 times faster than software running on a 1.5 GHz Intel Pentium machine.

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Approximate-min* constraint node updating for ldpc code decoding

Cited by 61 publications

References 9 publications

A Comparison of ARA- and Protograph-Based LDPC Block and Convolutional Codes

A Comparison of ARA- and Protograph-Based LDPC Block and Convolutional Codes

Different perspective and approach to implement adaptive normalised belief propagation-based decoding for low-density parity check codes

Reconfigurable acceleration for Monte Carlo based financial simulation

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