Approximation approach for timing jitter characterization in circuit simulators

Gourary, M.M.; Rusakov, S.G.; Ulyanov, S.L.; Zharov, M.M.; Gullapalli, K.K.; Mulvaney, B.J.

doi:10.1109/date.2003.1253602

Cited by 5 publications

(3 citation statements)

References 15 publications

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“…The method is based on the presentation of a circuit as linear time-varying (LTV) system and uses the spectral decomposition of noise stochastic process [9,12,13].…”

Section: Methodsmentioning

confidence: 99%

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Frequency Adjusting Technique for Transient Noise Analysis of Nonlinear Integrated Circuits

Gourary

Русаков

Ulyanov

et al. 2019

MES

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The paper discusses the nonlinear noise simulation problems in integrated circuits. The method of automatic varying the number of harmonics is presented to reduce computational efforts of transient noise simulation techniques based on spectral decomposition of stochastic process. The adaptive procedure provides the noise simulation of nonlinear circuits without need to specify number of noise harmonics before the analysis.

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“…The method is based on the presentation of a circuit as linear time-varying (LTV) system and uses the spectral decomposition of noise stochastic process [9,12,13].…”

Section: Methodsmentioning

confidence: 99%

“…After finding the value c for the given three points and substituting (13) into (14) we can obtain errors in subintervals [ωm,ωk]…”

Section: Frequency Adjusting Methods Approachmentioning

confidence: 99%

Frequency Adjusting Technique for Transient Noise Analysis of Nonlinear Integrated Circuits

Gourary

Русаков

Ulyanov

et al. 2019

MES

Self Cite

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“…By using a single or collocated delay lines to transport the reference signals required for averaging, our approach is tolerant to process, temperature and power supply variations of the distributed buffers in a clock network, which is a significant source of clock skew [45]. The non-local mismatch sources are limited to the adjacent clock drivers between taps.…”

Section: A Implementationmentioning

confidence: 99%

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

Chattopadhyay

Žilić

2012

IEEE Trans. VLSI Syst.

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We present a clock distribution network that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular, standard cell-based design approach that mitigates the effect of intra-die temperature and process variances. We route the clock line serially, using an averaging technique to eliminate skew between clock regions in a domain. Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays. Our clock network provides control over regional clock skews, can be used in beneficial skew applications and facilitates silicon-debug. Serial clocking permits the use of routing switches in the clock network and allows post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability. The system uses a closed-loop synchronization phase to combine the clock skew reduction of an actively synchronized clock network with an open-loop operating phase that minimizes power consumption like passive clock networks. Our clock network provides significant flexibility for application-specific integrated circuit, system-on-chip, and field-programmable gate-array designs, exhibiting good operating characteristics everywhere in the design envelope. Our silicon implementation achieves a maximum edge-to-edge uncertainty of 80 ps for regional clocks, which is roughly equal to the cycle-to-cycle jitter of the on-chip clock source.

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