APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement

Accurate wirelength estimation is desirable for VLSI circuit design. However, todays increasing design complexity incorporates greater complexity and hence requires a prior estimate of wirelength without performing exact routing. In this paper, we consider Y -routing, and propose a partitioningbased wirelength estimation scheme for multi-terminal nets. We try to find an optimum partition size of a multi-terminal net, and introduce a correction factor to accommodate wirelength variation for geometrical distribution of pin terminals on a layout. Our proposed method is simple and elegant, and yields reasonable solutions in little time. Experimental results with technology dependent benchmarks, and several industry test cases are encouraging.

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Partitioning-based wirelength estimation technique for Y-routing

Samanta

Rahaman

Dasgupta

2012

2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)

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Geometry Independent Wirelength Estimation Method in VLSI Routing

Sardar

Mondal

Samanta

2013

2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems

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APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement

Cited by 2 publications

References 19 publications

Partitioning-based wirelength estimation technique for Y-routing

Partitioning-based wirelength estimation technique for Y-routing

Geometry Independent Wirelength Estimation Method in VLSI Routing

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