Arbitrary Bit Generation and Correction Technique for Encoding QC-LDPC Codes with Dual-Diagonal Parity Structure

Yoon, Chanho; Choi, Eun-Young; Cheong, Minho; Lee, Sok-Kyu

doi:10.1109/wcnc.2007.127

Cited by 10 publications

(5 citation statements)

References 3 publications

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“…Yoon et al proposed a novel IR-QC-LDPC matrix H [35] and a responsive recursive accumulated algorithm for encoding. In IR-QC-LDPC codes, the parity-check matrix H can be partitioned into square sub-matrices of the size z×z.…”

Section: Ldpc Codesmentioning

confidence: 99%

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Implementation of encoder and decoder for LDPC codes based on FPGA

Cheng

Shen

Liao

et al. 2019

Journal of Systems Engineering and Electronics

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This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check (IR-QC-LDPC) codes, with a dual-diagonal parity structure. A normalized min-sum algorithm (NMSA) is employed for decoding. The whole verification of the encoding and decoding algorithm is simulated with Matlab, and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6% and 1.04%. Based on the results of simulation, multi-code rates are compatible with different basis matrices. Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array (FPGA). The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6% are realized based on FPGA.

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Section: Ldpc Codesmentioning

confidence: 99%

“…As Section 2 describes, (4) has a dual diagonal structure. Yoon et al [35] introduced a novel recursive accumulated algorithm and Liu et al implemented this method on an FPGA [36].…”

Section: Ldpc Encodingmentioning

confidence: 99%

Implementation of encoder and decoder for LDPC codes based on FPGA

Cheng

Shen

Liao

et al. 2019

Journal of Systems Engineering and Electronics

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“…From the structure of the base matrix we notice that, for both rates, the parity-check matrices of the codes have a dualdiagonal form, that is, contain two diagonals of symbols 1 in their rightmost part. This property can facilitate encoding, when accomplished through the parity-check matrix [11], without yielding the penalization in minimum distance that would be due to the inclusion of identity blocks. The same also occurs for the other base matrices provided by the…”

Section: Qc-ldpc Codes In Mobile Wimaxmentioning

confidence: 99%

Regular and Irregular Multiple Serially- Concatenated Multiple-Parity-Check Codes for Wireless Applications

Baldi

Cancellieri

Chiaraluce

et al. 2009

JCOMSS

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Multiple Serially-Concatenated Multiple-Parity-Check (M-SC-MPC) codes are a class of structured Low-Density Parity-Check (LDPC) codes, characterized by very simple encoding, that we have recently introduced. This paper evidences how the design of M-SC-MPC codes can be optimized for their usage in wireless applications. For such purpose, we consider some Quasi-Cyclic LDPC codes included in the mobile WiMax standard, and compare their performance with that of M-SCMPC codes having the same parameters. We also present a simple modification of the inner structure of M-SC-MPC codes that can help to improve their error correction performance by introducing irregularity in the parity-check matrix and increasing the length of local cycles in the associated Tanner graph. Our results show that regular and irregular M-SC-MPC codes, so obtained, can achieve very good performance and compare favorably with standard codes.

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“…But the larger gap makes the encoding complexity far from linear. A hardware efficient LDPC encoding scheme using arbitrary bit generation technique is shown in [13], [14] where the authors propose shared hardware architecture to reduce complexity. An ensemble based encoding scheme [17] is proposed in which the authors modify the code ensemble to force an ALT structure, thus eliminating the need for applying permutation of parity-check matrix of the code iteratively.…”

Section: Introductionmentioning

confidence: 99%

Linear encoding of LDPC codes using approximate lower triangulation with postprocessing

Islam

Kim

2009

2009 IEEE 20th International Symposium on Personal, Indoor and Mobile Radio Communications

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A new technique is proposed for efficient encoding of low density parity check (LDPC) codes using the concept of approximate lower triangulation (ALT). Parity check matrix is preprocessed and encoded in O(n) complexity. This encoding technique is applied in the IEEE 802.11n based H matrix where the complexity is compared with the Richardson algorithm. The proposed adaptive message length (AML) encoding scheme takes less than half number of computations compared to the Richardson scheme while keeping similar bit error rate (BER) performance.

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Arbitrary Bit Generation and Correction Technique for Encoding QC-LDPC Codes with Dual-Diagonal Parity Structure

Cited by 10 publications

References 3 publications

Implementation of encoder and decoder for LDPC codes based on FPGA

Implementation of encoder and decoder for LDPC codes based on FPGA

Regular and Irregular Multiple Serially- Concatenated Multiple-Parity-Check Codes for Wireless Applications

Linear encoding of LDPC codes using approximate lower triangulation with postprocessing

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