Arbitration Schemes for Multiprocessor Shared Bus

Bajaj, Preeti; Padole, Dinesh

doi:10.5772/16197

Cited by 3 publications

(5 citation statements)

References 15 publications

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“…Then a pseudo random number is generated to choose one of the competing masters to be the winner of the lottery, favoring masters that have a larger number of tickets, and grant access is issued to the chosen master for a certain number of bus cycles. The random number guarantees that there is no master will monopolize the sharing resource [6,9].…”

Section: B Lottery Bus Arbitrationmentioning

confidence: 99%

“…According to the type of the tickets, lottery algorithms are divided into two types: static lottery and dynamic lottery [6]. In the static lottery, as shown in Fig.…”

Section: B Lottery Bus Arbitrationmentioning

confidence: 99%

“…However, if the pseudo-random number is greater than the total tickets value, none of the masters will get access the bus. Moreover, the fixed ticket values in the static lottery algorithm give high chance to masters with high ticket values [6]. The limitation of the dynamic lottery algorithm is that the distribution of the ticket values is non-uniform [9].…”

Section: B Lottery Bus Arbitrationmentioning

confidence: 99%

“…The improvements on the bus arbitration protocols are performed to enhance some of the protocols' aspects, such as: the fairness degree, latency time, bandwidth utilization, responding to priorities, cost, and power consumption [6].…”

Section: Introductionmentioning

confidence: 99%

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A Bus Arbitration Scheme with an Efficient Utilization and Distribution

El-Kustaban¹,

Qahtan²

2017

ijacsa

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Abstract-Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to place several processors on the same chip die to get Chip Multiprocessor (CMP). The shared bus is the most common media used to connect these processors with each other and with the shared resources. Distributing the shared bus among the contention processors represents a critical issue that affects overall performance of the CMP. Optimal utilization with fair distribution of the shared bus represents another challenge. This paper introduces a bus arbitration scheme, which is an AgeBased Lottery (ABL) Arbitration that combines the lottery and age-based algorithms to overcome the shared bus challenges. The results show that the developed bus arbitration scheme maximizes the bus utilization and improves the distribution by at least 13.5% with an acceptable latency time comparing to the traditional bus arbitration schemes.

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Section: B Lottery Bus Arbitrationmentioning

confidence: 99%

“…According to the type of the tickets, lottery algorithms are divided into two types: static lottery and dynamic lottery [6]. In the static lottery, as shown in Fig.…”

Section: B Lottery Bus Arbitrationmentioning

confidence: 99%

Section: B Lottery Bus Arbitrationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Bus Arbitration Scheme with an Efficient Utilization and Distribution

El-Kustaban¹,

Qahtan²

2017

ijacsa

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“…The DataMultiplexer block will provide a prioritized Round-Robin arbitration [9], [10] in which each of the transmitters are assigned a specific number of DataWords that they can send during a full iteration of the arbiter.…”

Section: The Transmitter Unitmentioning

confidence: 99%

A flexible communication method for multi-FPGA based designs

Chirap¹,

Cret

2013

Proceedings of the 10th FPGAworld Conference

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High throughput applications have been widely used for deployment onto FPGAs. As the requirements for performance increase so does the challenge of integrating more complex algorithms into these platforms. This paper presents a flexible, low resource usage method which can be configured to integrate large designs into multiple FPGA chips using Xilinx's high-speed serial interfaces that minimize the performance penalty due to chip-to-chip communication. The proposed solution also provides a way of sharing the same data link for multiple applications, which offers valuable support for distributed FPGA applications with a minimal overhead and configurable bandwidth division. The impact of using this method inside a new application should not require complex architectural changes. The design was successfully validated and then applied onto a set of open-source cores.

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