Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms

Colaso, Adrian; Prieto, Pablo; Abad, Pablo; Gregorio, J.A.; Puente, Valentín

doi:10.1109/ipdps.2019.00037

Cited by 5 publications

(3 citation statements)

References 30 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…RTM's leakage power and capacity advantages give it a competitive edge over existing memory technologies, but the expensive shift operations present a daunting challenge. In this context, various techniques for RTM shift cost reduction have been proposed, such as runtime data swapping [25], [28], [36], data compression [26], [37], preshifting [18], [38], access port management [24], [25], [28], intelligent instruction [39], and data placement [2], [3]. For data placement, Chen et al in [3] present a heuristic appending data objects according to the adjacency information sequentially.…”

Section: Related Workmentioning

confidence: 99%

ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees

Hakert

Khan

Chen

et al. 2023

IEEE Trans. Comput.

View full text Add to dashboard Cite

Modern low power distributed systems tend to integrate machine learning algorithms. In resource-constrained setups, the execution of the models has to be optimized for performance and energy consumption. Racetrack memory (RTM) promises to achieve these goals by offering unprecedented integration density, smaller access latency, and reduced energy consumption. However, to access data in RTM, it needs to be shifted to the access port first. We investigate decision trees and develop placement strategies to reduce the total number of shifts in RTM. Decision trees allow profiling during training, resulting in tree paths' access probabilities. We map tree nodes to RTM so that the total number of shifts is minimal. Concretely, we present two different placement approaches: 1) where tree nodes are closely packed and placed uniformly in a single RTM location and 2) where decision tree nodes are decomposed to separate RTM blocks. We discuss theoretical cost models for both approaches, we formally prove an upper bound of 4× for the unified and an upper bound of 12× for the decomposed organization towards the optimal placement. We conduct a thorough experimental evaluation to compare our algorithms to the state-of-the-art placement strategies Our experimental evaluations show that the unified and decomposed solutions reduce the number of shifts by 58.1% and 80.1%, respectively, leading to a 53.8% and 46.3% reduction in the overall runtime and 52.6% and 61.7% reduction in the energy consumption, compared to a naive baseline.

show abstract

Section: Related Workmentioning

confidence: 99%

ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees

Hakert

Khan

Chen

et al. 2023

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…Other approaches focusing on L2 caches propose header management policies consisting of a hardware prefetcher to predict the next shift operation [11], data block compression schemes [46], and a dynamic adjustment of the number of active bits per racetrack according to the application demands [28]. With the aim to reduce the overhead of shifts, some works propose data placement strategies based on integer linear programming formulations [8,15,16,31] and genetic algorithms [14].…”

Section: Related Workmentioning

confidence: 99%

“…For instance, the shift latency of a 64-domain racetrack can be as long as 63 cycles in the worst case, assuming one cycle to shift a single domain [34], which is even higher than the Last-Level Cache (LLC) latency of modern processors (e.g., by 40 cycles in the Intel Skylake). Because of this fact, numerous research has focused on the LLC and concentrates on novel access header policies to minimize the impact of shift operations [7,11,15,19,28,34,46].…”

Section: Introductionmentioning

confidence: 99%

Fast-track cache

Tárrega

Valero

Lorente

et al. 2022

Proceedings of the 36th ACM International Conference on Supercomputing

View full text Add to dashboard Cite

First-level (L1) caches have been traditionally implemented with Static Random-Access Memory (SRAM) technology, since it is the fastest memory technology, and L1 caches call for tight timing constraints in the processor pipeline. However, one of the main downsides of SRAM is its low density, which prevents L1 caches to improve their storage capacity beyond a few tens of KB. On the other hand, the recent Domain Wall Memory (DWM) technology overcomes such a constraint by arranging multiple bits in a magnetic racetrack, and sharing a header to access those bits. Accessing a bit requires a shift operation to align the target bit under the header. Such shifts increase the final access latency, which is the main reason why DWM has been mostly used to implement slow last-level caches.This paper proposes a novel DWM-based L1 cache data array design, namely Fast-Track Cache (FTC), that allows L1 caches with bigger storage capacities while reducing the shift overhead thanks to an enhanced exploitation of spatial and temporal localities.Experimental results show that most FTC accesses do not require shifts. As a consequence, and due to its larger capacity, FTC improves the processor performance on average by 15% over a conventional SRAM memory subsystem and the state-of-the-art TapeCache architecture based on DWM. At the same time, energy savings are improved on average by 34% over the conventional design. CCS CONCEPTS• Hardware → Spintronics and magnetic technologies; Memory and dense storage.

show abstract