Architectural and physical design challenges for one-million gate FPGAs and beyond

“…To optimize a design, the designer must reevaluate design decisions, modify the code, retranslate the code, reexecute the new circuit, and iterate until constraints are met. These DTE iterations can require weeks or months of increased design time [7,8], because even if only minor change is made to the code, placement and routing may take hours or even days.…”

Section: Introductionmentioning

confidence: 99%

Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Wang

Stitt

Lam

et al. 2015

International Journal of Reconfigurable Computing

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Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many highperformance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD's prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

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“…With the advances in process technology, multimillion gate FPGAs have become available. A key issue that needs to be solved for the large-scale FPGAs to realize their full potential lies in the design of their routing architectures [11]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…This 0278-0070/01$10.00 © 2001 IEEE example shows that segmentation designs could deeply influence the routability of an FPGA. Rose and Hill [11] emphasized that segmentation distribution would become a key challenge in large-scale FPGA design. They pointed out that physical design for a large-scale FPGA would be difficult because the routing delays and resource utilization could not be handled well and, thus, it is hard to realize the full potential of a large-scale FPGA.…”

Section: Introductionmentioning

confidence: 99%

Matching-based algorithm for FPGA channel segmentation design

Chang

Lin

Wong

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Process technology advances have made multimillion gate field programmable gate arrays (FPGAs) a reality. A key issue that needs to be solved in order for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. Channel segmentation designs have been studied to some degree in much of the literature; the previous methods are based on experimental studies, stochastic models, or analytical analysis. In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a problem of finding the optimal segmentation architecture for two input routing instances and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient multilevel matching-based algorithm for general channel segmentation designs. Experimental results show that our method significantly outperforms the previous work. For example, our method achieves average improvements of 18.2% and 8.9% in routability in comparison with other work.

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Architectural and physical design challenges for one-million gate FPGAs and beyond

Cited by 24 publications

References 12 publications

A New Switch Block for Segmented FPGAs

A New Switch Block for Segmented FPGAs

Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Matching-based algorithm for FPGA channel segmentation design

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