Architectural enhancements for fast subword permutations with repetitions in cryptographic applications

McGregor, J.P.; Lee, R.B.

doi:10.1109/iccd.2001.955065

Cited by 26 publications

(16 citation statements)

References 14 publications

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“…However, computational tasks in digital signal processing, communication, computer graphics, and cryptography require that all of the information encoded in the input be preserved in the output. Some of those tasks are important enough to justify adding new microprocessor instructions to the HP PA-RISC (MAX and MAX-2), Sun SPARC (VIS), PowerPC (AltiVec), IA-32 and IA-64 (MMX) instruction sets [18,13]. In particular, new bit-permutation instructions were shown to vastly improve performance of several standard algorithms, including matrix transposition and DES, as well as two recent cryptographic algorithms Twofish and Serpent [13].…”

Section: Introductionmentioning

confidence: 99%

“…Some of those tasks are important enough to justify adding new microprocessor instructions to the HP PA-RISC (MAX and MAX-2), Sun SPARC (VIS), PowerPC (AltiVec), IA-32 and IA-64 (MMX) instruction sets [18,13]. In particular, new bit-permutation instructions were shown to vastly improve performance of several standard algorithms, including matrix transposition and DES, as well as two recent cryptographic algorithms Twofish and Serpent [13]. Bit permutations are a special case of reversible functions, that is, functions that permute the set of possible input values.…”

Section: Introductionmentioning

confidence: 99%

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Synthesis of reversible logic circuits

Shende

Prasad

Markov

et al. 2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

454

305

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Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input-output line-pairs (temporary storage channels). We prove constructively that every even permutation can be implemented without temporary storage using NOT, CNOT and TOFFOLI gates. We describe an algorithm for the synthesis of optimal circuits and study the reversible functions on three wires, reporting the distribution of circuit sizes. Finally, in an application important to quantum computing, we synthesize oracle circuits for Grover's search algorithm, and show a significant improvement over a previously proposed synthesis algorithm.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Synthesis of reversible logic circuits

Shende

Prasad

Markov

et al. 2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

454

305

View full text Add to dashboard Cite

show abstract

“…This is a significant result since previously arbitrary n-bit bit permutations took O(n) cycles. Even with our recent proposals of permutation instructions [5][9] [10][11] [12], this took at least O(log(n)) cycles. We show how a different 64-bit dynamically-specified permutation can be achieved every cycle by a 4-way superscalar processor with datarich MOMR execution.…”

Section: Discussionmentioning

confidence: 99%

“…A third approach involves specifying the order of the indices of the source bits in the permuted result. Examples are PPERM [11], and SWPERM and SIEVE [12]. The XBOX instruction [3] is similar to PPERM.…”

Section: Past Workmentioning

confidence: 99%

Validating Word-Oriented Processors for Bit and Multi-word Operations

Lee

Yang

Shi

2004

Advances in Computer Systems Architecture

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Abstract. We examine secure computing paradigms to identify any new architectural challenges for future general-purpose processors. Some essential security functions can be provided by different classes of cryptography algorithms. We identify two categories of operations in these algorithms that are not common in previous general-purpose workloads: bit operations within a word and multi-word operations. Both challenge the basic word orientation of processors. We show how very complex bit-level operations, namely arbitrary bit permutations within a word, can be achieved in O(1) cycles, rather than O(n) cycles as in existing RISC processors. We describe two solutions: one using only microarchitecture changes, and another with Instruction Set Architecture (ISA) support. We generalize our solutions to define datarich execution with MOMR (Multi-word Operands Multi-word Result) functional units. This can address both challenges, leveraging available resources in typical processors with minimal additional cost. Thus we validate the basic word-orientation of processor architectures, since they can also provide superior performance for both bit and multi-word operations needed by cryptographic processing.

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“…We propose two new instructions to efficiently support permutations with repetitions of 1-bit or multiple-bit subwords: swperm and sieve [13]. Using these instructions, we can dynamically specify permutations with repetitions during program execution rather than force the permutations to be statically encoded at compile-time.…”

Section: Permutation Instructionsmentioning

confidence: 99%

Architectural techniques for accelerating subword permutations with repetitions

McGregor

Lee

2003

IEEE Trans. VLSI Syst.

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Abstract-We propose two new instructions, swperm and sieve, that can be used to efficiently complete an arbitrary bit-level permutation of an -bit word with or without repetitions. Permutations with repetitions are rearrangements of an ordered set in which elements may replace other elements in the set; such permutations are useful in cryptographic algorithms. On a four-way superscalar processor, we can complete an arbitrary 64-bit permutation with repetitions of 1-bit subwords in 11 instructions and only four cycles using the two proposed instructions. For subwords of size 4 bits or greater, we can perform an arbitrary permutation with repetitions of a 64-bit register in a single cycle using a single swperm instruction. This improves upon previous results by requiring fewer instructions to permute 4-bit or larger subwords packed in a 64-bit register and fewer execution cycles for 1-bit subwords on wide superscalar processors. We also demonstrate that we can accelerate the performance of the popular DES block cipher using the proposed instructions. We obtain a DES performance improvement of at least 55% in constrained embedded environments and an improvement of 71% on a four-way superscalar processor when applying DES as a cryptographic hash function.

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Architectural enhancements for fast subword permutations with repetitions in cryptographic applications

Abstract: Abstract

Cited by 26 publications

References 14 publications

Synthesis of reversible logic circuits

Synthesis of reversible logic circuits

Validating Word-Oriented Processors for Bit and Multi-word Operations

Architectural techniques for accelerating subword permutations with repetitions

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