Architecture and applications of the HiPAR video signal processor

Ronner, K.; Kneip, J.

doi:10.1109/76.486420

Cited by 14 publications

(5 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is visualized in Fig. 2 by marking pixels (6, 0), (6, 1), (6,2), and (6, 3) with crosses. The pixels are stored in the memory modules 2, 0, 2, and 0 and would require sequential accesses.…”

Section: Example Parallel Memory Architecturementioning

confidence: 98%

“…Let's say that we want the pixels inside the 2 × 2 square access format in order (3, 1), (4, 1), (3,2), and (4, 2). Since the physical locations of the memory modules are fixed, the permutation network is needed to switch the data from the memory modules in the order S 1 , S 2 , S 3 , and S 0 .…”

Section: Example Parallel Memory Architecturementioning

confidence: 99%

“…In general, internal parallel memory architectures with versatile access schemes are not widely used by processors. However, a highly parallel DSP (HiPAR-DSP) has employed parallel memory architecture as an internal data memory with versatile access formats [1][2][3]. HiPAR-DSP is a VLIW-controlled ASIMD RISCarchitecture with four or sixteen data paths.…”

Section: Parallel Memory Solutionmentioning

confidence: 99%

“…In Fig. 2, 2 × 2 square is marked as an access format covering the pixels (3, 1), (4, 1), (3,2), and (4, 2). The signal F selects the access format, and the signal r the place (i, j) for the access format.…”

Section: Example Parallel Memory Architecturementioning

confidence: 99%

“…Stages represented by the arrows on the right refer to (1). Memory module address calculation, (2). Parallel memory access, and (3).…”

Section: Performance Comparison Of the Memory Architecturesmentioning

confidence: 99%

See 4 more Smart Citations

On Design of Parallel Memory Access Schemes for Video Coding

Tanskanen

Creutzburg

Niittylahti

2005

J VLSI Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.

show abstract

Section: Example Parallel Memory Architecturementioning

confidence: 98%

Section: Example Parallel Memory Architecturementioning

confidence: 99%