A data path array has been designed as core of a digital signal processor architecture for image processing applications. Data supply to data paths and exchange of data among data paths isperformed via an on-chip shared memory with two-dimenswnal address space. Distribution of data onto these memory blocks enables simultaneous, coflict-free access to the shared memory by the data paths. Data that is accessed concurrently is addressed in shape of a generalized matrix, i.e. a two-dimensional array with address-offsets between neighbors. Additionally, each data path has autonomous addressing capabilities to a distributed local cache memory. The combination of shared memory communication among the data paths and address and control autonomy of the array elements leads to the powerfi core of a high-performance DSP, that is completed by a RISC-style controller and a DMA-unit for data transfer. Simulation results proved, that the processor will show high performance on a wide field of image processing applications. Assuming 100 MHz clock frequency for a 4 X 4 array, the processor will perform a 1024 samples complex FFT within 33 ps including data IIO. The Hough transform of a 512 x 512 pel image with 30% blackpels is performed within 66ms,asswning 7 bitquuntizationfor the angle and11 bitquantization for the radius, thus achieving a sustained arithmetic performance of 2.8 Giga operations per second (GOPS).

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