A data path array with shared memory as core of a high performance DSP

Abstract

A data path array has been designed as core of a digital signal processor architecture for image processing applications. Data supply to data paths and exchange of data among data paths isperformed via an on-chip shared memory with two-dimenswnal address space. Distribution of data onto these memory blocks enables simultaneous, coflict-free access to the shared memory by the data paths. Data that is accessed concurrently is addressed in shape of a generalized matrix, i.e. a two-dimensional array with address-offsets between neighbors. Additionally, each data path has autonomous addressing capabilities to a distributed local cache memory. The combination of shared memory communication among the data paths and address and control autonomy of the array elements leads to the powerfi core of a high-performance DSP, that is completed by a RISC-style controller and a DMA-unit for data transfer. Simulation results proved, that the processor will show high performance on a wide field of image processing applications. Assuming 100 MHz clock frequency for a 4 X 4 array, the processor will perform a 1024 samples complex FFT within 33 ps including data IIO. The Hough transform of a 512 x 512 pel image with 30% blackpels is performed within 66ms,asswning 7 bitquuntizationfor the angle and11 bitquantization for the radius, thus achieving a sustained arithmetic performance of 2.8 Giga operations per second (GOPS).

Multimedia rectangularly addressable memory

“…Such an approach is limited by the implementable registers size and high routing complexity -in contrast to the current proposal, which allows arbitrary larger data to be accessed. Compared to [1], [3], [5]- [8], [11], [12], [14], our scheme enables higher scalability and lower number of memory modules. This directly affects the design complexity, which has been proven to be very low in our case.…”

“…Therefore, it is slower and requires more memory modules than our proposal. A memory organization, capable of accessing square blocks, aligned into memory modules was described in [11]. The same scheme was used for the implementation of the matrix memory of the first version of HiPAR-DSP [12].Besides the restriction to square accesses only, that memory system uses a redundant number of modules, due to additional DSP-specific access patterns considered.…”

On Design of Parallel Memory Access Schemes for Video Coding

“…Block diagram of the proposed parallel memory architecture. Stages represented by the arrows on the right refer to (1). Memory module address calculation, (2).…”

“…In general, internal parallel memory architectures with versatile access schemes are not widely used by processors. However, a highly parallel DSP (HiPAR-DSP) has employed parallel memory architecture as an internal data memory with versatile access formats [1][2][3]. HiPAR-DSP is a VLIW-controlled ASIMD RISCarchitecture with four or sixteen data paths.…”

Realization of a programmable parallel DSP for high performance image processing applications

“…The requirement of a high bandwidth access to shared data is solved by the matrix memory architecture. Internally, the data are distributed to nine single ported memory banks by use of a distribution function that provides a conflict free access to data from any address of it' s virtual 2D address space [3]. The generic structure of the processor and the implementation of a stack mechanism made the porting of the GNU C++ compiler feasible.…”