Architecture and hardware for scheduling gigabit packet streams

Krishnamurthy, R.; Yalamanchill, S.; Schwan, Karsten; West, Richard

doi:10.1109/conect.2002.1039257

Cited by 10 publications

(18 citation statements)

References 8 publications

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“…Usually, a hash function needs to do several processing tasks on the input data which requires a lot of time for serial processing. The increase in the speed of internet requires significant speed-up for most of internet processes; from running on serial processing on software to parallel processing on hardware [5].…”

Section: Related Workmentioning

confidence: 99%

An FPGA hardware architecture of Nilsimsa fingerprinting algorithm

Monemi

Mohamed

Marsono

2011

International Conference on Electrical, Control and Computer Engineering 2011 (InECCE)

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Nilsimsa algorithm is a very effective spam fingerprinting technique. This spam fingerprinting algorithm is formulated for software implementation. In this paper, we present an FPGA hardware architecture of the modified form of Nilsimsa algorithm which has similar accurate with the original softwaretargeted algorithm. The modification results in hardware resources reduction and execution time speed up. The implemented algorithm works at 123 MHz frequency and has a throughput of 1 byte per 2 clock cycles (494 Megabits per second). Our system also needs an extra 512 clock cycles after receiving the entire of the message to compute the Nilsimsa fingerprint. This means the minimum time for computing the fingerprint of a message with the size of 10 Kbytes is 167 μ s, which is equal to 5988 emails per second. For 100 MHz clock, our proposed architecture is 1400 times faster compared to implementation on 32-bit general-purpose embedded processor, and 24 times faster than the implementation on a modern CPU running on 2.64 GHz clock.

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Section: Related Workmentioning

confidence: 99%

An FPGA hardware architecture of Nilsimsa fingerprinting algorithm

Monemi

Mohamed

Marsono

2011

International Conference on Electrical, Control and Computer Engineering 2011 (InECCE)

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“…The MAX module takes log 2 n cycles and has a building cost in LUTs area of O(n), where n is the maximum number of VCs per output link. It is possible to reduce the area of this module to either O( 2 n ) or O(log 2 n), building a recirculating shuffle-exchange network as in [9]. Nevertheless, the resulting critical data path and complexity is then increased due to the presence of new multiplexers.…”

Section: Network Interfacementioning

confidence: 99%

“…Previous efforts [11,13,9] have proposed priority queuing architectures for switches and NICs. Our architecture is inspired on link schedulers designed for the MMR router.…”

Section: Introductionmentioning

confidence: 99%

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A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers

Claver

Canseco

Agustí

et al. 2006

Parallel and Distributed Processing and Applications

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Abstract. In this paper we present the architecture and implementation of a hardware NIC scheduler to guarantee QoS on servers for high speed LAN/SAN. Our proposal employs a programmable logic device based on an FPGA in order to store and update connection states, and to decide what data stream is to be sent next. The network architecture is connection-oriented and reliable, based on credit flow control. The architecture scales from 4 to 32 streams using a Xilinx Virtex 2000E. It supports links with speeds in the order of Gbps while, maintaining the delay and jitter constrains for the QoS streams.

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“…The BA architecture experiences more logic "spread" because of the need to route winners and losers and shows higher clock rate depreciation than the WR architecture. Our Area/Clock rate results for the BA architecture for Virtex I are from [14]. …”

Section: Window-constrained Architecturementioning

confidence: 99%

ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers

Krishnamurthy

Yalamanchili

Schwan

et al.

12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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ShareStreams (Scalable Hardware Architectures forStream Schedulers) is a unified hardware architecture for realizing a range of wire-speed packet scheduling disciplines for output link scheduling. This paper presents opportunities to exploit parallelism, design issues, tradeoffs and evaluation of the FPGA hardware architecture for use in switch network interfaces. The architecture uses processor resources for queueing & data movement and FPGA hardware resources for accelerating decisions and priority updates. The hardware architecture stores state in Register base blocks, stream service attributes are compared using single-cycle decision blocks arranged in a novel single-stage recirculating network. The architecture provides effective mechanisms to trade hardware complexity for lower execution-time in a predictable manner. The hardware realized in a Virtex-I and Virtex-II FPGA can meet the packet-time requirements of 10Gbps links for 256 stream queues with window-constrained scheduling disciplines. The hardware can schedule 1536 stream queues with priority-class/fair-queueing scheduling disciplines using 16 service-classes to meet 10Gbps packet-times.

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Architecture and hardware for scheduling gigabit packet streams

Cited by 10 publications

References 8 publications

An FPGA hardware architecture of Nilsimsa fingerprinting algorithm

An FPGA hardware architecture of Nilsimsa fingerprinting algorithm

A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers

ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers

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