2008 International Conference on Field Programmable Logic and Applications 2008
DOI: 10.1109/fpl.2008.4630028
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Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching

Abstract: This paper describes the efficient implementation of a Frame Aggregation Unit that gathers Ethernet packets in G.709 containers. This design has the capacity to handle 10Gbps links, to perform classification based on 24-byte header, and includes a highly pipelined Queue Manager to cope with the considered rates while a specific scheduler controls the quality of service per core network flow. The obtained results as regards area and performance for an actual working FPGA Virtex-4 implementation are provided whi… Show more

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Cited by 4 publications
(1 citation statement)
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“…A dynamic memory scheme is proposed in [21] to reduce packet loss in frame assembly nodes with limited buffer length. In the proposed scheme, a frame assembly node uses a module, called the packet queue manager (PQM), to adjust the size of each VOQ dynamically according to the traffic distribution.…”
Section: Relevant Workmentioning
confidence: 99%
“…A dynamic memory scheme is proposed in [21] to reduce packet loss in frame assembly nodes with limited buffer length. In the proposed scheme, a frame assembly node uses a module, called the packet queue manager (PQM), to adjust the size of each VOQ dynamically according to the traffic distribution.…”
Section: Relevant Workmentioning
confidence: 99%