Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors

Abstract

Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload.The recent HEVC standard, which offers several high-level parallelization strategies, is an important application that can benefit from an implementation tailored for the low-power AMPs present in many current mobile or hand-held devices. In this scenario, we present an architecture-aware implementation of an HEVC decoder that embeds a criticality-aware scheduling strategy tuned for a Samsung Exynos 5422 system-on-chip furnished with an ARM R big.LITTLE TM AMP. The performance and energy efficiency of our solution is further enhanced by exploiting the NEON TM vector engine available in the ARM big.LITTLE architecture. Experimental results expose a 1080p real-time HEVC decoding at 24 frames/sec, and a reduction of energy consumption over 20%.

An efficient model for quantifying the interaction between structural properties of software and hardware in the ARM big.LITTLE architecture

“…In order to evaluate the performance behavior of big.LITTLE cores, we also use High Efficiency Video Coding (HEVC) as our target test application. The reason for using HEVC comes from the growing adaptation of big.LITTLE in SoCs targeting mobile devices, where video‐based media applications such as content streaming are increasingly becoming popular . The HEVC algorithm also manifests significant complexity as well as diversity of operations ranging from memory‐intensive operations (motion estimation), compute‐intensive operations (prediction, rate‐distortion optimization, transformation), and hybrid combinations.…”

Quantifying the Interaction Between Structural Properties of Software and Hardware in the ARM Big.LITTLE Architecture

“…In order to evaluate performance behavior of big.LITTLE cores we also use High Efficiency Video Coding (HEVC) [11] as our target test application. The reason to use HEVC comes from the growing adaptation of big.LITTLE in SoCs targeting mobile devices, where video based media applications such as content streaming is increasingly popular [12]. HEVC algorithm also manifests significant complexity as well as diversity of operations ranging from memory intensive operations (motion estimation), compute intensive operations (prediction, rate-distortion optimization, transformation) and hybrid combinations.…”