Architecture design exploration of three-dimensional (3D) integrated DRAM

Anigundi, Rakesh; Sun, Hongbin; Lu, Jian‐Qiang; Rose, K.; Zhang, Tong

doi:10.1109/isqed.2009.4810274

Cited by 21 publications

(9 citation statements)

References 9 publications

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“…Therefore, to access data in each frame simultaneously using the per-row DRAM-to-logic data delivery strategy, the 3D stacked DRAM has 2 Â 6= 12 banks and an aggregate data I/O width of 16 Â 8 Â 6 =768 bits (i.e., 768 TSVs). For DRAM performance modeling and energy estimation, we use the 3D DRAM design strategy presented in [7] that has been implemented based upon the widely used memory modeling tool CACTI [8]. All the DRAM modeling is carried out at the 65 nm technology node.…”

Section: Simulation Resultsmentioning

confidence: 99%

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators

Liu

Zhang

2010

Signal Processing: Image Communication

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Section: Simulation Resultsmentioning

confidence: 99%

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators

Liu

Zhang

2010

Signal Processing: Image Communication

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“…Therefore, the overall system consists of B ranks grouped in vertical. All the banks in a 3D vertical rank share a single TSV bus, which can largely relax the TSV pitch constraints [13].…”

Section: D Memorymentioning

confidence: 99%

HPC Accelerators with 3D Memory

Ujaldón

2016

2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Co

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Abstract-After a decade evolving in the High Performance Computing arena, GPU-equipped supercomputers have conquered the top500 and green500 lists, providing us unprecedented levels of computational power and memory bandwidth. This year, major vendors have introduced new accelerators based on 3D memory, like Xeon Phi Knights Landing by Intel and Pascal architecture by Nvidia. This paper reviews hardware features of those new HPC accelerators and unveils potential performance for scientific applications, with an emphasis on Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) used by commercial products according to roadmaps already announced.

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“…Therefore, the overall system is composed of N bank of vertical ranks. All the banks in a 3D vertical rank share a single TSV bus, which can largely relax the TSV pitch constraints [5].…”

Section: B 3d-dram Architecture Modelingmentioning

confidence: 99%

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing

Zhu

Akin

Sumbul

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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Abstract-This paper introduces a 3D-stacked logic-in-memory (LiM) system that integrates the 3D die-stacked DRAM architecture with the application-specific LiM IC to accelerate important data-intensive computing. The proposed system comprises a fine-grained rank-level 3D die-stacked DRAM device and extra LiM layers implementing logic-enhanced SRAM blocks that are dedicated to a particular application. Through silicon vias (TSVs) are used for vertical interconnections providing the required bandwidth to support the high performance LiM computing. We performed a comprehensive 3D DRAM design space exploration and exploit the efficient architectures to accelerate the computing that can balance the performance and power. Our experiments demonstrate orders of magnitude of performance and power efficiency improvements compared with the traditional multithreaded software implementation on modern CPU.

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Architecture design exploration of three-dimensional (3D) integrated DRAM

Cited by 21 publications

References 9 publications

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators

HPC Accelerators with 3D Memory

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing

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