Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

Muhammad, Sayed T.; El-Moursy, Magdy A.; El-Moursy, Ali A.; Hamed, Hesham F. A.

doi:10.1016/j.jpdc.2016.12.019

Cited by 3 publications

(1 citation statement)

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“…Congestion Information Calculation. In [26], a delay model is proposed in which input and output buffer delay and calculation of the router delay are not considered. In the CFPA routing algorithm, a new model of delays is proposed [20].…”

Section: Methodsmentioning

confidence: 99%

Congestion‐Aware Routing Algorithm for NoC Using Data Packets

Ahmad

Sethi

Ullah

et al. 2021

Wireless Communications and Mobile Computing

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Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

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Section: Methodsmentioning

confidence: 99%