Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

Abstract

In current reconfigurable architectures, the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density (smaller area footprint) makes the problem even more important. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. However, the benefits of such integration technology have not been sufficiently explored yet. In this paper, we propose a software-supported methodology for exploring and evaluating alternative interconnection schemes for 3D FPGAs. In order to support the proposed methodology, three new CAD tools were developed (part of the 3D MEANDER Design Framework). During our exploration, we study the impact of vertical interconnection between functional layers in a number of design parameters. More specifically, the average gains in operation frequency, power consumption, and wirelength are 35%, 32%, and 13%, respectively, compared to existing 2D FPGAs with identical logic resources. Also, we achieve higher utilization ratio for the vertical interconnections compared to existing approaches by 8% for designing 3D FPGAs, leading to cheaper and more reliable devices.

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

“…The gain obtained in performance is due the optimized wire delay at higher levels of the Tree interconnect by re-arranging them in the 2 layer 3D chip with the Tree interconnection between level 3 and 4 is realized using TSVs. Similarly the comparison with 3D Mesh-based FPGA [6] with 32% gain shows, 3D Tree-based FPGA outperform in all benchmarks and an overall performance gain of 53% recorded in the experiment.…”

“…To evaluate the performance of the proposed 3D MFPGA architecture, we place and route the largest set MCNC 3 benchmark circuits, and compare with the 3D Mesh-based FPGA architecture [6]. The netlist is partitioned into tree based cluster nets attributing randomly to each cluster a position inside the owner.…”

“…A design framework for 3D FPGA architecture level exploration methodology was presented in [6]. It includes an additional feature to explore the vertical interconnect distribution, however this leads to usage of 2D and 3D switch blocks intermittently, which may lead to number of design and manufacturing issues.…”

Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology

“…According to [11], [12] the SBs has been the most areaconsuming unite compared to other design elements in 2D FPGAs and this situation is becoming even worse in 3D LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB UMSB UMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB OUT UMSB UMSB UMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB DMSB FPGAs because the TSVs are located in 3D-SBs. Although the design and manufacturing engineers are trying to reduce TSV dimensions, the minimum feature size on the die is also shrinking.…”

“…The first one is developed by monolithic stacking, whereby the active devices are lithographically built in between metal layers [21] and the second type is evolved from original 2D structure by extending the 2D switch boxes (SBs) to 3D ones [11], [12]. So far, there are two design and exploration frameworks targeting 3D FPGA architectures: the three-dimensional place and route (TPR) [12] and 3D MEANDER [11]. In TPR, all SBs are assumed to be 3D-SBs and the number of TSVs is assumed to be unlimited, which is an impractical assumption as far as design and manufacturing of 3D chips is concerned.…”