Architecture Level Optimizations for Kummer Based HECC on FPGAs

Gallin, Gabriel; Çelik, Türkü Özlüm; Tisserand, Arnaud

doi:10.1007/978-3-319-71667-1_3

Cited by 2 publications

(1 citation statement)

References 23 publications

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“…We designed several HECC hardware accelerators using our HTMM unit and various configurations of the architecture (see [9] for more details). We compared the 256-bit ECC solution from [6] and 2 of our accelerators for µKummer HECC (named H1 and H2).…”

Section: Htmm Usage In Hecc Based On µKummermentioning

confidence: 99%

Hyper-threaded multiplier for HECC

Gallin

Tisserand

2017

2017 51st Asilomar Conference on Signals, Systems, and Computers

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Abstract-Modular multiplication is the most costly and common operation in hyper-elliptic curve cryptography. Over prime fields, it uses dependent partial products and reduction steps. These dependencies make FPGA implementations with fully pipelined DSP blocks difficult to optimize. We propose a new multiplier architecture with hyper-threaded capabilities. Several independent multiplications are handled in parallel for efficiently filling the pipeline and overlapping internal latencies by independent computations. It increases the silicon efficiency and leads to a better area / computation time trade-off than current state of the art. We use this hyper-threaded multiplier into small accelerators for hyper-elliptic curve cryptography in embedded systems.

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Section: Htmm Usage In Hecc Based On µKummermentioning

confidence: 99%

Hyper-threaded multiplier for HECC

Gallin

Tisserand

2017

2017 51st Asilomar Conference on Signals, Systems, and Computers

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Generation of Finely-Pipelined GF(P) Multipliers for Flexible Curve Based Cryptography on FPGAs

Gallin

Tisserand²

2019

IEEE Trans. Comput.

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In this paper, we present modular multipliers for hardware implementations of (hyper)-elliptic curve cryptography on FPGAs. The prime modulus P is generic and can be configured at run-time to provide flexible circuits. A finelypipelined architecture is proposed for overlapping the partial products and reductions steps in the pipeline of hardwired DSP slices. For instance, 2, 3, or 4 independent multiplications can share the hardware resources at the same time to overlap internal latencies. We designed a tool, distributed as open source, for generating VHDL codes with various parameters: width of operands, number of logical multipliers per physical one, speed or area optimization, possible use of BRAMs, target FPGA. Our modular multipliers lead to, at least, 2 times faster as well as 2 times smaller circuits than state of the art operators.

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Architecture Level Optimizations for Kummer Based HECC on FPGAs

Cited by 2 publications

References 23 publications

Hyper-threaded multiplier for HECC

Hyper-threaded multiplier for HECC

Generation of Finely-Pipelined GF(P) Multipliers for Flexible Curve Based Cryptography on FPGAs

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