Hyper-threaded multiplier for HECC

Abstract

Abstract-Modular multiplication is the most costly and common operation in hyper-elliptic curve cryptography. Over prime fields, it uses dependent partial products and reduction steps. These dependencies make FPGA implementations with fully pipelined DSP blocks difficult to optimize. We propose a new multiplier architecture with hyper-threaded capabilities. Several independent multiplications are handled in parallel for efficiently filling the pipeline and overlapping internal latencies by independent computations. It increases the silicon efficiency and leads to a better area / computation time trade-off than current state of the art. We use this hyper-threaded multiplier into small accelerators for hyper-elliptic curve cryptography in embedded systems.

Generation of Finely-Pipelined GF(P) Multipliers for Flexible Curve Based Cryptography on FPGAs

“…As the results from [19] are very good, we reproduced their multiplier on more FPGAs and other sizes. In our first work [2], we only implemented the 128-bit version of the multiplier from [19]. Since this first work, we added a 256bit version of their multiplier.…”

“…1. We used this s + 1 cycles schedule in our previous work [2]. In Section III-F, we propose a new improvement to remove this extra cycle in tasks 1 and 3.…”

“…In [2], we proposed finely-pipelined modular multipliers (FPMMs) for 128-bit HECC designed by hand for a few FPGAs (the URL is given in the references Section). Below, we extend these results with new optimizations, a wider G. Gallin is with CNRS, IRISA UMR 6074, University Rennes and INRIA Centre Rennes -Bretagne Atlantique, France.…”

“…The parameter space is so wide that we decided to design a tool, distributed as open source [3], to generate optimized FPMMs in VHDL. Compared to [2], our tool allows us to explore multipliers with:…”

“…• flexible prime P defined at run time (P was fixed in [2]); • fewer DSP slices and a shorter computation time; • a higher ratio between the operations throughput and the area cost compared to state of the art solutions; • a higher frequency (close to the maximum allowed by the technology, e.g. 502 MHz upon 550 MHz in Virtex-5); • a larger parameter space at design time: width of operands, number of logical multipliers per physical one, more supported FPGAs, potential use of BRAMs, and new area/speed optimizations.…”