Architecture-level synthesis for automatic interconnect pipelining

Abstract

For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined global interconnects. In this paper we present an architecture-level synthesis solution to support automatic pipelining of on-chip interconnects. Specifically, we extend the recently proposed Regular Distributed Register (RDR) micro-architecture to support interconnect pipelining. We formulate a novel global interconnect sharing problem for global wiring minimization and show that it is polynomial time solvable by transformation to a special case of the real-time scheduling problem. Experimental results show that our approach matches or exceeds the RDR-based approach in performance, with a significant wiring reduction of 15% to 21%.

Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture

“…The first set of seven DFGs are extracted from MediaBench [16], then scheduled, bound, and placed in a 3×3 RDR-based architecture. The synthesis results for four different architecture-algorithm pairs, RDR/MCAS [7], RDR-Pipe/MCAS-Pipe [8], RDR-GRS/ILP [9] and RDR-GRS/RSS, are shown in Table I. The second and third column show the number of nodes and data transfers of the test case, respectively.…”

“…Therefore, the number of required wires and register pairs in RDR/MCAS is lower-bounded by the number of the maximum possible concurrent data transfers at a cycle. Later, an extension named the RDR-Pipe/MCAS-Pipe is proposed in [8]. RDR-Pipe allows data transfers with the identical source-destination pair to share the same wires by inserting extra pipeline registers as intermediate stops.…”

Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining

“…In fact, since the feature size of CMOS devices is continuously decreasing and more functionality is integrated on a chip, the length and number of global interconnects tend to increase [7]. Consequently, in future nanometer designs it will be impossible to carry signal across the chip within a single clock cycle and multi-cycle cross-chip communication becomes necessary, so that cross-chip interconnect is removed from all the timing constraints, and the chip speed is determined by the most critical intra-block/local combinational path, in order to continue employing higher frequencies [4], [5]. Insertion of sequential elements in interconnects lines -a concept that has become known as interconnect pipelining − is one feasible solution for modern nanometer technologies.…”

“…In [11], a floor-planning methodology, which considers interconnect pipelining and its impact on performance using the IPC sensitivity models is described. The authors of [5] explored the possibilities of sharing interconnect pipelining to reduce wiring overheads. And, [6] provides two techniques to deal with the short path constraint of latch based wire pipelining.…”

Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining

“…Nanometer scale process technologies enable integration of billions of transistors with multiple-gigahertz operating frequencies [4]. However, continuous shift towards design in nanometer scale has been increasing the gap between device and wire delays, especially the global interconnect delays, which do not scale well with the feature size [8].…”