Architecture of a VLSI instruction cache for a RISC

Patterson, David A.; Garrison, Phil; Hill, Mark D.; Lioupis, D.; Nyberg, Chris; Sippel, Tim; Dyke, Korbin Van

doi:10.1145/800046.801645

Cited by 46 publications

(22 citation statements)

References 8 publications

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“…Block-disabling has been proposed by [15], [19] to increase processor yield and is used by modern processors [13] to continue operation in the presence of permanent-errors. In this work we consider it for lowvoltage operation.…”

Section: Block-disabling and Victim Cachingmentioning

confidence: 99%

Performance-effective operation below Vcc-min

Ladas

Sazeides

Desmet

2010

2010 IEEE International Symposium on Performance Analysis of Systems &Amp; Software (ISPASS)

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Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been proposed recently as a mean to reverse this trend. The goal of this paper is to minimize the performance loss due to reduced cache capacity when operating below Vcc-min. A simple method is proposed: disable faulty blocks at low voltage. The method is based on observations regarding the distributions of faults in an array according to probability theory. The key lesson, from the probability analysis, is that as the number of uniformly distributed random faulty cells in an array increases the faults increasingly occur in already faulty blocks. The probability analysis is also shown to be useful for obtaining insight about the reliability implications of other cache techniques.For one configuration used in this paper, block disabling is shown to have on the average 6.6% and up to 29% better performance than a previously proposed scheme for low voltage cache operation. Furthermore, block-disabling is simple and less costly to implement and does not degrade performance at or above Vcc-min operation. Finally, it is shown that a victim-cache enables higher and more deterministic performance for a block-disabled cache.

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Section: Block-disabling and Victim Cachingmentioning

confidence: 99%

Performance-effective operation below Vcc-min

Ladas

Sazeides

Desmet

2010

2010 IEEE International Symposium on Performance Analysis of Systems &Amp; Software (ISPASS)

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“…An early proposal treated accesses to a faulty cache line as a miss [13], i.e. memory lines which mapped to faulty cache lines were never brought into the cache.…”

Section: Related Workmentioning

confidence: 99%

Customizable Fault Tolerant Caches for Embedded Processors

Ramaswamy

Yalamanchili

2006

2006 International Conference on Computer Design

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Abstract-The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embedded processors. Concurrently, intra-die and inter-die process variation at future technology nodes will cause defect-free yield to drop sharply unless mitigated. This paper focuses on an architectural technique to configure cache designs to be resilient to memory cell failures brought on by the effects of process variation. Profile-driven re-mapping of memory lines to cache lines is proposed to tolerate failures while minimizing degradation in average memory access time (AMAT) and thereby significantly boosting performance-based die yield beyond that which can be achieved with current techniques. For example, with 50% of the number of cache lines faulty, the performance drop quantified by increase in AMAT using our technique is 12.5% compared to 60% increase in AMAT using existing techniques.

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“…The Branch Target Buffer technique has been evaluated consistently as the most effective branch prediction strategy [Lee andSmith 1984, McFarling andHennessy 1986]: one observes that even in RISC machines, where the use of software techniques has been prevalent, the use of Branch Target Buffers has not been completely ruled out [Patterson et al 1983]. It has become the preferred prediction strategy in more recent high-performance machines such as the IBM 3090 [Tucker 1986] and NEC's SX machines [Watanabe, Katayama, and Iwaya 1986].…”

Section: '9mentioning

confidence: 99%

“…Their weakness is that not only do they require considerable ingenuity on the part of the compiler writer but also that in spite of this they are not always applicable; it is sometimes the case that compiler-generated code simply cannot be manipulated in the manner indicated by the above example. Indeed, the designers of the Berkley RISCs have not found the use of hardware techniques, in the form of an instruction cache with some branch prediction, to be unreasonable [Patterson et al 1983].…”

Section: '9mentioning

confidence: 99%

On the design and performance of conventional pipelined architectures

Topham

Omondi

1988

J Supercomput

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Pipelining is a widely used technique for implementing architectures that have inherent temporal parallelism when there is an operational requirement for high throughput. Many variations on the basic theme have been proposed, with varying degrees of success. The aim of this paper is to present a critical review of conventional pipelined architectures and put some well-known problems in sharp relief. It is argued that conventional pipelined architectures have underlying limitations that can only be dealt with by adopting a different view of pipelining. These limitations are explained in terms of discontinuities in the flow of instructions and data, an d representative machines are examined in support of this argument. In a companion paper [Topham, Omondi and Ibbett, 1988] we examine an alternative approach to the design of pipelined architectures and introduce an alternative theory of pipelining, which we call Context Flow.

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Architecture of a VLSI instruction cache for a RISC

Cited by 46 publications

References 8 publications

Performance-effective operation below Vcc-min

Performance-effective operation below Vcc-min

Customizable Fault Tolerant Caches for Embedded Processors

On the design and performance of conventional pipelined architectures

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