Architecture support for accelerator-rich CMPs

Cong, Jason; Ghodrat, Mohammad Ali; Gill, Michael; Grigorian, Beayna; Reinman, Glenn

doi:10.1145/2228360.2228512

Cited by 90 publications

(94 citation statements)

References 22 publications

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“…This approach is complementary to our work, as our accelerators are essentially C functions with traditional function-call and memory-access semantics. Similarly, recent research by Cong et al has shown much potential for performance and energy improvement via architectural support in accelerator-rich CMPs [41].…”

Section: Related Workmentioning

confidence: 92%

Accelerating vision and navigation applications on a customizable platform

Cong

Grigorian

Reinman

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computationally demanding solutions, it is challenging to achieve high performance without sacrificing the fidelity of results or otherwise consuming excessive amounts of energy. Our goal then is to accelerate the applications in this domain to meet real-time performance constraints while simultaneously reducing energy consumption and avoiding degradation in the quality of results. To achieve this domain-specific acceleration, we model a customizable hardware platform based on the 3D integration of a Field-Programmable Gate Array (FPGA) atop a standard chip multiprocessor (CMP) with Through-Silicon Vias (TSVs) used for communication between the two layers. Furthermore, partial automation of accelerator creation using C-to-RTL tools allows for analysis of a wide range of candidates. In this work, we mathematically characterize viable accelerator candidates, describe ideal application code for acceleration, and outline a dynamic-programming-based methodology for selecting an optimal set of candidates. Our results yield an overall speedup and energy reduction of 9.56X along with a 94X EDP reduction for the domain. Finally, we investigate the effects of various interconnect models on our performance improvements. Overall, our proposed system is shown to be highly efficient in both accelerating performance and saving energy for compute-intensive applications in this domain.

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Section: Related Workmentioning

confidence: 92%

Accelerating vision and navigation applications on a customizable platform

Cong

Grigorian

Reinman

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

Self Cite

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“…In this respect, the X-FILES are related to similar extensions or frameworks like HiPPAI [29] and ARC [30]. However, the needs of HiPPAI and ARC are distinctly different from the X-FILES.…”

Section: A Accelerator Interfaces and Managementmentioning

confidence: 99%

“…We further subdivide memory transfers into those involving virtual or physical addresses. While this would normally be a hard, design-time decision (as is common with similar accelerator interfaces [29], [30]) we prefer to not restrict the generality of the X-FILES during definition. Instead, and as with register/memory mode, we take the view that these transfer modes should be exposed to agents (like the hardware designer, library writer, compiler, or OS) that can make the most informed decision regarding interface choice.…”

Section: Introductionmentioning

confidence: 99%

Towards General-Purpose Neural Network Computing

Eldridge¹,

Waterland

Seltzer³

et al. 2015

2015 International Conference on Parallel Architecture and Compilation (PACT)

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Abstract-Machine learning is becoming pervasive; decades of research in neural network computation is now being leveraged to learn patterns in data and perform computations that are difficult to express using standard programming approaches. Recent work has demonstrated that custom hardware accelerators for neural network processing can outperform software implementations in both performance and power consumption. However, there is neither an agreed-upon interface to neural network accelerators nor a consensus on neural network hardware implementations. We present a generic set of software/hardware extensions, X-FILES, that allow for the generalpurpose integration of feedforward and feedback neural network computation in applications. The interface is independent of the network type, configuration, and implementation. Using these proposed extensions, we demonstrate and evaluate an example dynamically allocated, multi-context neural network accelerator architecture, DANA. We show that the combination of X-FILES and our hardware prototype, DANA, enables generic support and increased throughput for neural-networkbased computation in multi-threaded scenarios. These diverse implementations and usage cases drive fascinating innovation. As diversity increases, however, a gap is developing between these innovations and the state of today's hardware and software. I. INTRODUCTION1 As such it is worth con-

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“…We share their attention to memory reuse, but take the alternative approach of integrating accelerators as NoC nodes, enabling GP-CPUs to reuse the accelerator's private memory blocks as NUCA slices. Our NoC-based coupling of accelerators and GP-CPUs is similar to the one proposed by Cong et al [4], although they do not consider memory reuse and focus instead on architectural support for accelerator abstraction.…”

Section: Related Workmentioning

confidence: 99%

“…Given the predicted fall of multicore scaling at the hands of dark silicon [5], superior efficiency via specialization has materialized as a compelling solution toward sustaining performance gains [16]; once restricted to embedded systems, accelerators are currently seeing wider exposure (e.g., [3]), and many-accelerator architectures are in the research agenda ( [4], [13]). …”

Section: Introductionmentioning

confidence: 99%

Accelerator Memory Reuse in the Dark Silicon Era

Cota

Mantovani

Petracca

et al. 2014

IEEE Comput. Arch. Lett.

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Abstract-Accelerators integrated on-die with General-Purpose CPUs (GP-CPUs) can yield significant performance and power improvements. Their extensive use, however, is ultimately limited by their area overhead; due to their high degree of specialization, the opportunity cost of investing die real estate on accelerators can become prohibitive, especially for general-purpose architectures. In this paper we present a novel technique aimed at mitigating this opportunity cost by allowing GP-CPU cores to reuse accelerator memory as a non-uniform cache architecture (NUCA) substrate. On a system with a last level-2 cache of 128kB, our technique achieves on average a 25% performance improvement when reusing four 512 kB accelerator memory blocks to form a level-3 cache. Making these blocks reusable as NUCA slices incurs on average in a 1.89% area overhead with respect to equally-sized ad hoc cache slices.

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Architecture support for accelerator-rich CMPs

Cited by 90 publications

References 22 publications

Accelerating vision and navigation applications on a customizable platform

Accelerating vision and navigation applications on a customizable platform

Towards General-Purpose Neural Network Computing

Accelerator Memory Reuse in the Dark Silicon Era

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