Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Underwood,; Hemmert,; Ulmer, Hanno

doi:10.1109/sc.2006.13

Cited by 14 publications

(8 citation statements)

References 17 publications

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“…One popular algorithm is: (1) perform the forward FFT on the signal; (2) make the components of negative frequencies zero; (3) calculate the inverse Fast Fourier Transform (iFFT) to obtain the analytic signal; and (4) take the imaginary portion as the HT of the original signal. Since the FPGA has been proven to be far more efficient in embedding the FFT versus its microprocessor/Digital Signal Processor counterpart [32], the selection of this algorithm may be rational and provides an exact solution.…”

Section: Embedding Hilbert Transform (Ht)mentioning

confidence: 99%

Embedded Algorithms Within an FPGA to Classify Nonlinear Single-Degree-of-Freedom Systems

Jones

Pei

2009

IEEE Sensors J.

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This study is a significant advancement of this team's proof-of-concept study on using field-programmable gate arrays (FPGAs) in wireless sensing for structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform. An effort is presented herein to embed algorithms to process nonlinear time series by entirely using an FPGA, while an ongoing effort is to pursue the development of an FPGA and microprocessor co-design for a more extended and robust version of this study.The Hilbert Transform (HT) and a backbone curve technique are the centerpiece to extract instantaneous characteristics of a displacement time history from a SDOF system under free vibration. Critical design issues are carefully considered including required approximation accuracy, constraints imposed by limited hardware resources, timing in the execution of the hardware design, and data representations in a fixed-point design environment. An automation of the classification of three basic types of SDOF systems (including linear, hardening and softening) are implemented for wireless transmission of processed results. An off-the-shelf high-level abstraction tool along with the MATLAB/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. Extensive validation using simulated data is conducted for every step/stage of the design as well as major built-in functions adopted from the hardware design tool.The contribution of this study includes (1) enabling the functionality of a full hardware design for an enhanced computational efficiency in wireless structural health monitoring and (2) achieving balance between computational efficiency and resource utilization for onboard data processing especially when non-high-end FPGA products are targeted for practical consideration in structural health monitoring.

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Section: Embedding Hilbert Transform (Ht)mentioning

confidence: 99%

Embedded Algorithms Within an FPGA to Classify Nonlinear Single-Degree-of-Freedom Systems

Jones

Pei

2009

IEEE Sensors J.

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“…For FPGAs to effectively participate in computations, adequate communication paths are required. I/O bottlenecks between the processor and FPGA frequently limit reconfigurable systems from greater performance [Underwood et al 2006]. Given the need for parallelism, scalability, and throughput, research is converging to on-chip networks as the connection architecture of choice [Dally and Towles 2001;Kapre et al 2006;Mak et al 2006;Pionteck et al 2007].…”

Section: Benefits and Challengesmentioning

confidence: 99%

A packet-switched network architecture for reconfigurable computing

Lloyd

Snell

2009

ACM Trans. Embed. Comput. Syst.

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A packet-switched network architecture named Qnet and programming interface is presented that simplifies the integration of reconfigurable computing modules within a Field-Programmable Gate Array (FPGA). Qnet provides an abstraction layer to the designer of FPGA accelerator modules that hides the complexities of the system, while supporting a high degree of parallelism and performance. The architecture facilitates system design with pluggable, reusable modules. A network protocol is described that supports a three-party communication scheme between an initiator, a sender and a receiver. This protocol allows a master device to manage the state of other devices and the data flow within the system. An example using a high-level language is given. The Qnet architecture opens the computational power of FPGAs to computer scientists and software developers. ACM Reference Format:Lloyd, S. and Snell, Q. 2009. A packet-switched network architecture for reconfigurable computing.

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“…Underwood et al proposed a technique to predict execution time of FFT on FPGAs [13]. Similar to us, they construct a performance model of FFT by dividing the total execution into several sub steps, and derive the model parameters from profiling results.…”

Section: Related Workmentioning

confidence: 99%

An efficient, model-based CPU-GPU heterogeneous FFT library

Ogata

Endo

Maruyama

et al. 2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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General-Purpose computing on Graphics ProcessingUnits (GPGPU) is becoming popular in HPC because of its high peak performance. However, in spite of the potential performance improvements as well as recent promising results in scientific computing applications, its real performance is not necessarily higher than that of the current high-performance CPUs, especially with recent trends towards increasing the number of cores on a single die. This is because the GPU performance can be severely limited by such restrictions as memory size and bandwidth and programming using graphics-specific APIs. To overcome this problem, we propose a model-based, adaptive library for 2D FFT that automatically achieves optimal performance using available heterogeneous CPU-GPU computing resources. To find optimal load distribution ratios between CPUs and GPUs, we construct a performance model that captures the respective contributions of CPU vs. GPU, and predicts the total execution time of 2D-FFT for arbitrary problem sizes and load distribution. The performance model divides the FFT computation into several small sub steps, and predicts the execution time of each step using profiling results. Preliminary evaluation with our prototype shows that the performance model can predict the execution time of problem sizes that are 16 times as large as the profile runs with less than 20% error, and that the predicted optimal load distribution ratios have less than 1% error. We show that the resulting performance improvement using both CPUs and GPUs can be as high as 50% compared to using either a CPU core or a GPU.

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Architectures and APIs: Assessing Requirements for Delivering FPGA Performance to Applications

Cited by 14 publications

References 17 publications

Embedded Algorithms Within an FPGA to Classify Nonlinear Single-Degree-of-Freedom Systems

Embedded Algorithms Within an FPGA to Classify Nonlinear Single-Degree-of-Freedom Systems

A packet-switched network architecture for reconfigurable computing

An efficient, model-based CPU-GPU heterogeneous FFT library

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