Reconfigurable computing leveraging field programmable gate arrays (FPGAs) is one of many accelerator technologies that are being investigated for application to high performance computing (HPC). Like most accelerators, FPGAs are very efficient at both dense matrix multiplication and FFT computations, but two important aspects of how to deliver that performance to applications have received too little attention. First, the standard API for important compute kernels hides parallelism from the system. Second, the issue of system architecture is virtually never addressed. This paper explores both issues and their implications for applications. We find that high bandwidth, low latency connectivity can be important, but the right API can be even more important.

This paper discusses a two-level compilation scheme used for generating high-speed binary image morphology pipelines from a textual description of the algorithm. The first-level compiler generates a generic morphology machine which is customized for the specified set of instructions by the second-level compiler. Because the generic machine is reused, we are able to avoid long synthesis times and achieve compile times similar to software compile times, while still achieving a 10X speed-up over the software implementation.