AREA and power optimized multipliers with minimum leakage

Abstract

In this work, we designed a 10 transistor full adder for low power which is used in the implementation of different types of multipliers. All these multipliers are compared for different technologies 90nm, 70nm, 50nm. A power gating technique is used by placing an MTCMOS cell is used at fine grain level so as to minimize the leakage power. Multiplier is an essential arithmetic component for any DSP application, such as filtering and fast Fourier transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. Two Components contribute to the power dissipation in CMOS circuits. The Static dissipation is due to leakage current, while dynamic power dissipation is due to switching transient current as well as charging and discharging of load capacitances.

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

“…The analytical expression for (Wp/Wn) of each comparator is determined by equating the pull up and pull down saturation currents as equation (1) [14], [15], [16], [18].…”

Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

“…To achieve optimal sizing for each transistor in SIS comparator scheme is very much time consuming. The analytical expression for (W p /W n ) of each comparator is determined by equating the pull up and pull down saturation currents as equation 1[14], [15], [16], [18].…”

“…The various dynamic parameters for all ADCs are also calculated using the equations (15) -(21) [29], [36] and are tabulated in Table V. Offset error = Real Transition -Ideal Transition (15) Offset in LSB = Offset Error/ One LSB (16) Full Scale Error = Real last transition -Ideal last transition (17) Gain error = Average code width (LSB size) = Real last transition -First transition/2(2 n -1 -1) Table 5. Dynamic Parameters For ADCs In LSB…”