Area efficient architectures for information integrity in cache memories

Kim, Seongwoo; Somani, Arun K.

doi:10.1109/isca.1999.765955

Cited by 22 publications

(3 citation statements)

References 12 publications

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“…Their energy consumption is high, especially when data locality is low and the number of write-backs is large. In [20] a small cache for saving check bits or replicas is proposed. In this scheme, a large amount of the dirty data remains unprotected if data locality is low.…”

Section: Related Workmentioning

confidence: 99%

CPPC

Manoochehri

Annavaram

Dubois

2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

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Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist in other memory levels. While conventional error correcting codes can protect write-back caches, it has been shown that they are expensive in terms of area and power. This paper proposes a new reliable write-back cache called Correctable Parity Protected Cache (CPPC) which adds error correction capability to a parityprotected cache. For this purpose, CPPC augments a write-back parity-protected cache with two registers: the first register stores the XOR of all data written to the cache and the second register stores the XOR of all dirty data that are removed from the cache. CPPC relies on parity to detect a fault and then on the two XOR registers to correct faults. By a novel combination of byte shifting and parity interleaving CPPC corrects both single and spatial multi-bit faults to provide a high degree of reliability. We compare CPPC with one-dimensional parity, SECDED (Single Error Correction Double Error Detection) and two-dimensional parity-protected caches. Our simulation results show that CPPC provides a high level of reliability while its overheads are less than the overheads of SECDED and two-dimensional parity.

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Section: Related Workmentioning

confidence: 99%

CPPC

Manoochehri

Annavaram

Dubois

2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

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“…Plenty of research has been done in inventing schemes to reduce the overheads associated with error codes [46,47,248,254,[273][274][275][276]. We highlight the major features for reducing the overheads related to error codes for protecting caches:…”

Section: Mechanismmentioning

confidence: 99%

“…Another variant [274] proposed to use a small cache for saving check bits for ECC or replicated cache lines. Techniques protecting the dirty cache lines in a cache can be further benefited by employing policies such as eager writeback to reduce the number of dirty cache lines in the cache [243,262,263].…”

Section: Mechanismmentioning

confidence: 99%

Soft error mitigation techniques for future chip multiprocessors

Upasani

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The sustained drive to downsize the transistors has reached a point where device sensitivity against transient faults due to neutron and alpha particle strikes a.k.a soft errors has moved to the forefront of concerns for next-generation designs. Following Moore's law, the exponential growth in the number of transistors per chip has brought tremendous progress in the performance and functionality of processors. However, incorporating billions of transistors into a chip makes it more likely to encounter a soft soft errors. Moreover, aggressive voltage scaling and process variations make the processors even more vulnerable to soft errors. Also, the number of cores on chip is growing exponentially fueling the multicore revolution. With increased core counts and larger memory arrays, the total failure-in-time (FIT) per chip (or package) increases. Our studies concluded that the shrinking technology required to match the power and performance demands for servers and future exa- and tera-scale systems impacts the FIT budget. New soft error mitigation techniques that allow meeting the failure rate target are important to keep harnessing the benefits of Moore's law. Traditionally, reliability research has focused on providing circuit, microarchitecture and architectural solutions, which include device hardening, redundant execution, lock-step, error correcting codes, modular redundancy etc. In general, all these techniques are very effective in handling soft errors but expensive in terms of performance, power, and area overheads. Traditional solutions fail to scale in providing the required degree of reliability with increasing failure rates while maintaining low area, power and performance cost. Moreover, this family of solutions has hit the point of diminishing return, and simply achieving 2X improvement in the soft error rate may be impractical. Instead of relying on some kind of redundancy, a new direction that is growing in interest by the research community is detecting the actual particle strike rather than its consequence. The proposed idea consists of deploying a set of detectors on silicon that would be in charge of perceiving the particle strikes that can potentially create a soft error. Upon detection, a hardware or software mechanism would trigger the appropriate recovery action. This work proposes a lightweight and scalable soft error mitigation solution. As a part of our soft error mitigation technique, we show how to use acoustic wave detectors for detecting and locating particle strikes. We use them to protect both the logic and the memory arrays, acting as unified error detection mechanism. We architect an error containment mechanism and a unique recovery mechanism based on checkpointing that works with acoustic wave detectors to effectively recover from soft errors. Our results show that the proposed mechanism protects the whole processor (logic, flip-flop, latches and memory arrays) incurring minimum overheads. La nanotecnología ha continuado avanzando durante las últimas décadas al ritmo marcado por la ley de Moore, que dice que los transistores reducen su tamaño en un 50% cada dos años. Esta reducción en tamaño ha permitido que los transistores sean cada vez más rápidos y que consuman menos energía. Sin embargo, este avance tecnológico se enfrenta ahora al problema de la vulnerabilidad de estos pequeños transistores, sobre todo al impacto de las partículas (soft errors). Por otro lado, el uso que se hace hoy en día de estos transistores los hace aún más vulnerables a los posibles impactos de partículas. La reducción del voltaje que se usa en los procesadores actuales, el incremento de número de procesadores que hay en los dispositivos actuales, las variaciones en el proceso de fabricación... todo ayuda a que las partículas que impactan en los transistores causes errores. Nuestros estudios concluyen que la tecnología que se necesita para poder crear los futuros supercomputadores terascale y exascale va a ser muy susceptible a los impactos de partículas, y que nuevas técnicas para detectar y corregir los errores que causan van a ser imprescindibles. Las soluciones que se usan en la actualidad, basadas en modificación de circuitos y del diseño de los procesadores no van a poder usarse en los futuros superocomputadores terascale y exascale a un coste razonable. Una nueva clase de solución que se está investigando es la de detectar los impactos de las partículas, una solución totalmente opuesta a las direcciones anteriores basadas en detectar los errores que los impactos causaban. Nuestra solución consiste en poner un conjunto de detectores en el silicio que detectarían todos los impactos de partículas que potencialmente pudieran causar errores. Una vez el impacto es detectado, si fuera necesario aplicaríamos soluciones para recuperarnos del error que hubiera podido causar. En nuestro trabajo nos centramos en sensores acústicos. La tesis propone mecanismos que nos permiten detectar y localizar los impactos de partículas basados en estos sensores acústicos. Demostramos como se pueden usar para proteger los procesadores, lógica y memoria. También proponemos una solución que nos permite contener y recuperarnos de los errores que los impactos de partículas causan una vez se detectan a través de nuestros sensores. Los resultados demuestran que el coste para proteger los futuros supercomputadores terascale y exascale es razonable y suficiente.

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