Area-efficient FPGA-based FFT processor

Sansaloni, T.; Perez-Pascual, A.; Valls, Javier

doi:10.1049/el:20030892

Cited by 20 publications

(12 citation statements)

References 3 publications

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“…Further work has been done in implementing FFT cores for FPGAs [8], [10], [11], [3], [9] which can be scaled according to user-specified parameters, including the well regarded Spiral Project [9]. Beyond the radix 2 and 4 Cooley-Tukey seen in the Xilinx implementation, Pease and Fast Hartley Transforms have been implemented in order to achieve a specific tradeoff with regards to performance and resource utilisation [11], [8].…”

Section: Latency-resource Trading Fft Implementations On the Fpgamentioning

confidence: 99%

“…Another important feature of the previous work has been to identify strategies for implementations that may be scaled according to the needs of the end-user [8], [10], [3], [9]. It was also shown that making use of a higher level description language allowed for quicker development and prototyping of user-defined, yet optimised cores [11].…”

Section: Latency-resource Trading Fft Implementations On the Fpgamentioning

confidence: 99%

See 1 more Smart Citation

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

Inggs

Thomas

Winberg

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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This paper provides a novel way of trading increased resource utilisation for decreased latency when computing a single Discrete Fourier Transform on the FPGA. Analysis conducted on the Cooley-Tukey FFT optimisation shows that it increases the number of operations in the critical path of the transform computation. Consequentially an algorithm is proposed which allows control over the degree to which the Cooley-Tukey optimisation is utilised, trading between resource utilisation and absolute latency. The resource utilisation and latency results for the MyHDL implementation of the proposed algorithm upon the Rhino platform are provided which demonstrate that a practical Pareto curve has been established for a variety of dataset sizes. This implementation is also compared to Xilinx's FFT IP core, providing 14% better latency performance than the manufacturer's implementation albeit at a greater resource cost.

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Section: Latency-resource Trading Fft Implementations On the Fpgamentioning

confidence: 99%

Section: Latency-resource Trading Fft Implementations On the Fpgamentioning

confidence: 99%

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

Inggs

Thomas

Winberg

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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“…A recent work [17] describes an area-efficient architecture based on the use of a CORDIC operator [18] to perform the rotations, as we do in our work, but it does not target parallel implementations. A closer approach is the one presented in [19], but no comparison to other architectures is provided.…”

Section: Related Workmentioning

confidence: 99%

Implementing FFT-based digital channelized receivers on FPGA platforms

Sánchez

Garrido

López‐Vallejo

et al. 2008

IEEE Trans. Aerosp. Electron. Syst.

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This paper presents an in-depth study, implementation, and validation of Fast Fourier Transform Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to get faster real time in broadband digital receivers. To support the signal processing designer when implementing this kind of systems on FPGA platforms we have developed a design space exploration tool for FFT architectures.

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“…In the first algorithm implementation, we instantiate an array of 16 independent MACs (maximum number for available FPGA resources) and propagate the data through the array as shown in Figure 5.1 [9]. We explicitly encoded 16 MACs and the SRC compiler was allowed to implement the 16 MACs.…”

Section: Matrix-matrix Kernel Implementationmentioning

confidence: 99%

“…PSTSWM relies heavily on FFTs and thus computing these FFTs utilizing FPGA hardware is expected to provide significant performance advantages based on positive results with FFTs on FPGAs in real-time and DSP applications [8][9][10][11][12].…”

Section: Climate Modeling Kernel Implementationmentioning

confidence: 99%

Accelerating Scientific Applications with the SRC-6 Reconfigurable Computer: Methodologies and Analysis

Smith

Vetter

Liang

19th IEEE International Parallel and Distributed Processing Symposium

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Reconfigurable computing offers the promise of performing computations in hardware to increase performance and efficiency while retaining much of the flexibility of a software solution. Recently, the capacities of reconfigurable computing devices, like field programmable gate arrays, have risen to levels that make it possible to execute 64b floating-point operations. SRC Computers has designed the SRC-6 MAPstation to blend the benefits of commodity processors with the benefits of reconfigurable computing. In this paper, we describe our effort to accelerate the performance of several scientific applications on the SRC-6. We describe our methodology, analysis, and results. Our early evaluation demonstrates that the SRC-6 provides a unique software stack that is applicable to many scientific solutions and our experiments reveal the performance benefits of the system.

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Area-efficient FPGA-based FFT processor

Cited by 20 publications

References 3 publications

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

Implementing FFT-based digital channelized receivers on FPGA platforms

Accelerating Scientific Applications with the SRC-6 Reconfigurable Computer: Methodologies and Analysis

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