Area efficient high speed low power multiplier architecture for multirate filter design

Mariammal, K; Rani, S. P. Joy Vasantha; Kohila, T.

doi:10.1109/ice-ccn.2013.6528474

Cited by 5 publications

(1 citation statement)

References 16 publications

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“…At the beginning of the up converting chain, a complex heterodyne was applied when the signal sampling rate is very low while selecting the required number of stages according to the required frequency of the signal center. Mariammal, K. et al, [2] designed the multi-rate filter for multi-rate signal processing applications.…”

Section: Related Workmentioning

confidence: 99%

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

Manivannan¹,

Lakshminarasimman²,

Rani³

2019

IJITEE

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In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

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Section: Related Workmentioning

confidence: 99%