2016
DOI: 10.1166/jnan.2016.1285
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Area Efficient Layout Design of CMOS Device for Digital Circuit Applications

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Cited by 4 publications
(1 citation statement)
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“…The transistor used in proposed circuits is a single gate with overlapped structure as proposed earlier by V. K. Mishra and R. K. Chauhan, in which a CMOS inverter circuit was designed with the concept of placing n-MOS over p-MOS using the small insulated gap between them. 19,20 The integration of junctionless SOI into CMOS transistor technology is very beneficial for the digital circuit applications. The junctionless SOI transistor shows reduced leakage current and better I on /I off ratio at 18nm gate length.…”
mentioning
confidence: 99%
“…The transistor used in proposed circuits is a single gate with overlapped structure as proposed earlier by V. K. Mishra and R. K. Chauhan, in which a CMOS inverter circuit was designed with the concept of placing n-MOS over p-MOS using the small insulated gap between them. 19,20 The integration of junctionless SOI into CMOS transistor technology is very beneficial for the digital circuit applications. The junctionless SOI transistor shows reduced leakage current and better I on /I off ratio at 18nm gate length.…”
mentioning
confidence: 99%