Area-efficient mixed-radix variable-length FFT processor

Yang, Chen; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Ma, Cuimei

doi:10.1587/elex.14.20170232

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…The N‐point discrete Fourier transform (DFT) is defined as:

X ()(, k) = \sum_{n = 0}^{N - 1} x ()(, n) W_{N}^{k n}

The Cooley‐Tukey algorithm [7] calculates a long sequence DFT of size

N = M \times L

by dividing it into several smaller sequences DFT of size M and L.

({, \begin{matrix} 1em4pt \\ n = L \times m + l m = 0, 1, \dots M - 1; l = 0, 1, \dots L - 1 \\ k = M \times i + j i = 0, 1, \dots M - 1; j = 0, 1, \dots L - 1 \end{matrix})

Then, the DFT can be defined as

X ()(, i + M \times j) = \sum_{l = 0}^{L - 1} (][, X_{l} ()(, i) W_{N}^{i l}) W_{L}^{j l}

where

W_{L}^{j l}

is the twiddle factor and

X_{l} ()(, i)

is defined as

X ()(, i) = \sum_{m = 0}^{M - 1} x ()(, L \times m + l) W_{M}^{i m}

Based on the Cooley–Tukey algorithm, [8] proposed a mixed‐radix multipath delay feedback (MDF) FFT processor, where the FFT module is divided into multiple SDF modules and the complete result is calculated from the way of coupling. In Fig.…”

Section: Methodsmentioning

confidence: 99%

Dynamic partial reconfiguration scheme for fault‐tolerant FFT processor based on FPGA

Wei

Xie

et al. 2019

J. eng.

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“…The N‐point discrete Fourier transform (DFT) is defined as:

X ()(, k) = \sum_{n = 0}^{N - 1} x ()(, n) W_{N}^{k n}

The Cooley‐Tukey algorithm [7] calculates a long sequence DFT of size

N = M \times L

by dividing it into several smaller sequences DFT of size M and L.

({, \begin{matrix} 1em4pt \\ n = L \times m + l m = 0, 1, \dots M - 1; l = 0, 1, \dots L - 1 \\ k = M \times i + j i = 0, 1, \dots M - 1; j = 0, 1, \dots L - 1 \end{matrix})

Then, the DFT can be defined as

X ()(, i + M \times j) = \sum_{l = 0}^{L - 1} (][, X_{l} ()(, i) W_{N}^{i l}) W_{L}^{j l}

where

W_{L}^{j l}

is the twiddle factor and

X_{l} ()(, i)

is defined as

X ()(, i) = \sum_{m = 0}^{M - 1} x ()(, L \times m + l) W_{M}^{i m}

Section: Methodsmentioning

confidence: 99%

Dynamic partial reconfiguration scheme for fault‐tolerant FFT processor based on FPGA

Wei

Xie

et al. 2019

J. eng.

Self Cite

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“…As there are abundant digital signal processing (DSP) units in FPGA and support for efficient fixed-point computing, the system has strong processing capabilities [35]. On the other hand, because the FFT contains a large number of pixel-by-pixel operations [36,37], the communication between the processor and the external memory must be considered. The CS algorithm includes multiple matrix transposition operations, which increases the communication overheads of the processor and the memory, resulting in longer read and write times.…”

Section: Ddr3 Data Access Characteristics Analysismentioning

confidence: 99%

An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

2021

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With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.

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“…FFT processors are widely used in a variety of fields such as the radar signal processing, the remote sensing satellite, the image processing and communication. With the constant development of the technologies applied to these fields, higher requirements are put forward to the operation of FFT [1]. For example, to meet the strict specifications ultra‐wideband communication system, high‐throughput data should be processed in low latency [2].…”

Section: Introductionmentioning

confidence: 99%

“…Another 512‐point MDF FFT processor is designed in [10]. The radix‐2 4 ‐2 2 ‐2 3 algorithm is devised to reduce the complexity of twiddle factor multiplication [1].…”

Section: Introductionmentioning

confidence: 99%