With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

This paper presents a mixed-radix multipath delay feedback (MDF) FFT processor with variable-length. In order to minimize the number of occupied multipliers while supporting more flexible FFT length, a 4-parallel radix-2 3 mixed radix-2/3/4 architecture is adopted. In order to further optimize the area and power consumption, we make efforts in constant multiplier design, twiddle factor generation and butterfly units multiplexing. CSD multiplier is adopted to realize the constant factor multiplication in radix-2 3 and radix-3 butterfly. Only one CORDIC, several adders and multipliers are occupied to achieve the 4-parallel twiddle factor generation. A radix-2/3/4 multiplexing butterfly unit with simple control logic is also designed. The design is synthesized with 65 nm CMOS technology. Compared with previous works, the proposed design shows advantages in terms of area, power consumption, and processing latency.

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