Area efficient multiplier using NANO CMOS logic style

Sasikala, S.; Gomathi, S.; Chitra, M.; Nandhini, S.

doi:10.1063/5.0068616

Cited by 1 publication

(1 citation statement)

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“…Compared with static Si CMOS technology and reported 2D integrated circuits, a half adder has been realized by integrating two WSe 2 transistors, exhibiting high area efficiency. [12,19,20] Our carrier modulation method without the introduction of dopants can maintain the FET performance and it is independent of the gate modulation. This work provides a unique strategy to achieve the carrier modulation in 2D materials and shows a guideline for the design of single-transistor logic gates, emphasizing the relationship between the carrier polarity/density of the channel layer and the gate functionality.…”

Section: Introductionmentioning

confidence: 99%

Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area‐Efficient Computation

Bian

Miao

Zhang

et al. 2023

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2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area‐efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe2) field‐effect transistors (FETs) via introducing hexagonal boron nitride (h‐BN) as the interfacial dielectric layer is devised. By modulating the h‐BN thickness, the carrier type of WSe2 FETs has been switched from hole to electron. The ultrathin body of WSe2, combined with the effective polarity control, together contribute to the versatile single‐transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. The unique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.

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Section: Introductionmentioning

confidence: 99%