Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

Jung, Yongchul; Cho, Jaechan; Lee, Seongjoo; Jung, Yunho

doi:10.3390/electronics8121397

Cited by 7 publications

(5 citation statements)

References 32 publications

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“…where Tech is the process technology expressed in nanometers [39]. As shown in Table 4, the proposed accelerator exhibited an average area-speed efficiency (Gops/s/A norm ) 24% higher than XNE with fmap-level parallelism when operating at 300 MHz.…”

Section: Fpga Implementation Resultsmentioning

confidence: 98%

Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

et al. 2021

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Binary neural networks (BNNs) have attracted significant interest for the implementation of deep neural networks (DNNs) on resource-constrained edge devices, and various BNN accelerator architectures have been proposed to achieve higher efficiency. BNN accelerators can be divided into two categories: streaming and layer accelerators. Although streaming accelerators designed for a specific BNN network topology provide high throughput, they are infeasible for various sensor applications in edge AI because of their complexity and inflexibility. In contrast, layer accelerators with reasonable resources can support various network topologies, but they operate with the same parallelism for all the layers of the BNN, which degrades throughput performance at certain layers. To overcome this problem, we propose a BNN accelerator with adaptive parallelism that offers high throughput performance in all layers. The proposed accelerator analyzes target layer parameters and operates with optimal parallelism using reasonable resources. In addition, this architecture is able to fully compute all types of BNN layers thanks to its reconfigurability, and it can achieve a higher area–speed efficiency than existing accelerators. In performance evaluation using state-of-the-art BNN topologies, the designed BNN accelerator achieved an area–speed efficiency 9.69 times higher than previous FPGA implementations and 24% higher than existing VLSI implementations for BNNs.

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Section: Fpga Implementation Resultsmentioning

confidence: 98%

Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

et al. 2021

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“…In the FFT algorithm, if the input is assumed to be real, and in the interval [−1,1), the output is in the interval [−N, N). In practice, it can be expressed as FPX (16,14). To prevent data overflow and ensure the accuracy of data, 16-bit truncation is used in the final output butterfly stage.…”

Section: Analysis Of Experimental Resultsmentioning

confidence: 99%

High performance and resource efficient FFT processor based on CORDIC algorithm

Zhao

Liu

et al. 2022

EURASIP J. Adv. Signal Process.

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Fast Fourier Transform is widely used in communication and signal processing. I propose an improved multipath delay commutator pipelining architecture based on the radix-2 time decimation algorithm. By optimizing the intermediate data processing process and the first stage of pipelining, the architecture improves the system's computing speed and reduces the use of registers. I propose a multiplication scheme based on CORDIC and binary decomposition coding to realize complex number multiplication and constant multiplication and to eliminate the use of a multiplier. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

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“…However, these algorithms require the number of samples, the N FFT , to be equal to 2 a , where a is an integer. Nevertheless, it is usually not equal to the number of samples in the primary code period T. The solution is the zero-padding [25] of the r[t] and c[t] blocks of signal samples with N z zeroes.…”

Section: Acquisition-pcs Algorithm Zero-padding Algorithms and Bit Transition Problemmentioning

confidence: 99%

Joint Acquisition Estimator of Modern GNSS Tiered Signals Using Block Pre-Correlation Processing of Secondary Code

Svatoň

Vejrazka

2020

Sensors

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Objective is a joint primary and secondary code (SC) acquisition estimator of tiered Global Navigation Satellite Systems (GNSS) signals. The estimator is based on the Parallel Code Search algorithm (PCS) combined with the Single-Block-Zero-Padding (SBZP) and the Pre-correlation Coherent Accumulation (PCA). The PCA realizes the extension of the coherent integration time in front of the PCS. However, the PCS with the SBZP and the PCA is affected by a navigation/SC bit transition problem due to its cyclic property of a computed Cross-Ambiguity Function (CAF). This CAF is degraded by diverse parasitic fragments and is not directly applicable for an acquisition. A novel analysis of this mechanism and its impact is presented. Then, the proposed modified SBZP (mSBZP) modified PCA (mPCA) PCS estimator is constructed, which does not degrade the CAF. The mSBZP allows the use of the PCS algorithm in the presence of SC bit transition, while the mPCA decreases the number of PCS algorithm calculations by a factor of SC chip count due to SC pre-correlation processing. The algorithm has the same detection performance in comparison with conventional Double-Block-Zero-Padding (DBZP). However, it allows using the PCS of half-length with longer latency up to a factor of SC chip count.

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Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

Cited by 7 publications

References 32 publications

Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

High performance and resource efficient FFT processor based on CORDIC algorithm

Joint Acquisition Estimator of Modern GNSS Tiered Signals Using Block Pre-Correlation Processing of Secondary Code

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