Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation

Abstract

A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 µm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 µW, while the occupied area is 121x442 µm 2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is-133 dBV/ √ Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

A Low-Noise Chopper Amplifier with Offset and Low-Frequency Noise Compensation DC Servo Loop

“…Employing an additional noise-nonlinearity-cancelling loop significantly increases the complexity of circuit [9]. A switched-capacitor structure has advantages of accurate time constant and high voltage linearity, and it is also insensitive to temperature and process [6,[11][12][13]. However, the switched-capacitor technique suffers from its poor noise performance due to its charge injection, clock feed-through, and parasitic resistance [14,15].…”