2016
DOI: 10.1016/j.procs.2016.06.028
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Area Efficient VLSI Architecture for Square Root Carry Select Adder Using Zero Finding Logic

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Cited by 13 publications
(5 citation statements)
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“…The area and power values obtained from Cadence Encounter RTL compiler for the proposed design and the conventional architectures for data width ranging from 16-bit to 128-bit are shown in Fig.7 & Fig.8. [3] 7888.412 379428.727 SQRT-CSLA-BEC [3] 5868.246 300078.847 SQRT-CSLA-ZFC [5] 5269.538 227574.940 KSA-SQRT-CSLA [4] 7011.165 392390.364 KSA -SQRT-CSLA-BEC [6] 5641.933 325000.917 KSA-SQRT-CSLA-ZFC [7] 4928.933 255401.279 CSLA using Logic Optimization technique 4856.270 221876.170…”
Section: Fig7comparison Of Area In µM 2 For Different Adder Architementioning
confidence: 99%
See 1 more Smart Citation
“…The area and power values obtained from Cadence Encounter RTL compiler for the proposed design and the conventional architectures for data width ranging from 16-bit to 128-bit are shown in Fig.7 & Fig.8. [3] 7888.412 379428.727 SQRT-CSLA-BEC [3] 5868.246 300078.847 SQRT-CSLA-ZFC [5] 5269.538 227574.940 KSA-SQRT-CSLA [4] 7011.165 392390.364 KSA -SQRT-CSLA-BEC [6] 5641.933 325000.917 KSA-SQRT-CSLA-ZFC [7] 4928.933 255401.279 CSLA using Logic Optimization technique 4856.270 221876.170…”
Section: Fig7comparison Of Area In µM 2 For Different Adder Architementioning
confidence: 99%
“…One such technique is replacing Ripple carry adder with input carry is equal to "one" with Binary to Excess-1 converter in SQRT-CSLA [3]. The area is further reduced by minimization of gates in the design which can be designed by the usage of Zero Finding Logic (ZFC) [4]- [5]. But the area optimization is still considered as it decides the cost of the design.…”
Section: Introductionmentioning
confidence: 99%
“…3 Furthermore, Zero Finding Logic (ZFC) is employed in CSLA architecture for the purpose of area optimization. 4,5 But the combinational delay is very high because of XOR gates and AND gates. In Reference 6, CSLALOT is designed by using modified ripple carry adder for area optimization.…”
Section: Introductionmentioning
confidence: 99%
“…Ram et al [6] proposed "Area-Efficient Vedic Multiplier" in which BEC adder is used to reduce the area by replacing input carry value "1" by Binary to Excess code converter in the normal CSLA structure so that BEC adder requires only a small number of logic gates, moreover Vedic multiplier using BEC adder occupies the less memory when compared to conventional Vedic multiplier using CSLA. The area is further reduced by using zero finding logic in CSLA [7] instead of RCA with input carry is equal to 1, but with an increase in delay. Various designs of full adders using multiplexers and logic gates in CSLA architectures [8] proved that performance is efficient than conventional architectures.…”
Section: Introductionmentioning
confidence: 99%