Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication

Khan, Safiullah; Lee, Wai-Kong; Khalid, Ayesha; Majeed, Abdul; Hwang, Seong Oun

doi:10.1109/les.2022.3185265

Cited by 7 publications

(7 citation statements)

References 9 publications

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“…This shows that Cryptensor can flexibly support multiple security level using the same hardware. The standalone co-processor proposed by Khan et al [34] is 5.6× faster than the proposed Cryptensor, for the ees1499ep1 parameter. However, Cryptensor achieves better throughput to area efficiency (2.38) compared to Khan et al [34] (1.69).…”

Section: Evaluation On Polynomial Convolutionmentioning

confidence: 87%

“…The standalone co-processor proposed by Khan et al [34] is 5.6× faster than the proposed Cryptensor, for the ees1499ep1 parameter. However, Cryptensor achieves better throughput to area efficiency (2.38) compared to Khan et al [34] (1.69). Our architecture uses lesser LUT resources due to the efficient STA architecture.…”

Section: Evaluation On Polynomial Convolutionmentioning

confidence: 87%

“…al. [34] that is only at 111.45Mhz. Based on the experimental result, we see that although Cryptensor consumes more computational cycles, it can still be compact in area and operates at a higher operating frequency, thus achieving a more area-time efficient design.…”

Section: Evaluation On Polynomial Convolutionmentioning

confidence: 90%

“…Several accelerator designs targeting NTRU polynomial convolution were proposed recently ( [33], [34]). Farahmand et al [33] proposed a high-speed architecture that uses a lot of hardware resource, which is more suitable for deployment in high-end server.…”

Section: E Related Workmentioning

confidence: 99%

“…Farahmand et al [33] proposed a high-speed architecture that uses a lot of hardware resource, which is more suitable for deployment in high-end server. On the other hand, the architecture proposed by Khan et al [34] targets low area consumption, which is more suitable for implementation on sensor nodes. These two work are highly optimized for NTRU polynomial convolution but do not support other operations (e.g., CNN).…”

Section: E Related Workmentioning

confidence: 99%

See 4 more Smart Citations

Cryptensor: A Resource-Shared Co-processor to Accelerate Convolutional Neural Network and Polynomial Convolution

See¹,

Ng²,

Tan³

et al. 2022

Preprint

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<p>Practical deployment of convolutional neural net?work (CNN) and cryptography algorithm on constrained devices are challenging due to the huge computation and memory requirement. Developing separate hardware accelerator for AI and cryptography incur large area consumption, which is not desirable in many applications. This paper proposes a viable solution to this issue by expressing the CNN and cryptography as Generic-Matrix-Multiplication (GEMM) operations and map them to the same accelerator for reduced hardware consumption. A novel systolic tensor array (STA) design was proposed to reduce the data movement, effectively reducing the operand registers by 2×. Two novel techniques, input layer extension and polynomial factorization, are proposed to mitigate the under-utilization issue found in existing STA architecture. Additionally, the Tensor Processing Element (TPE) is fused using DSP unit to reduce the Look-Up Table (LUT) and Flip-Flops (FF) consumption for implementing multipliers. On top of that, a novel memory efficient factorization technique is proposed to allow computation of polynomial convolution on the same STA. Experimental results show that Cryptensor achieved 22.3% better throughput for VGG-16 implementation on XC7Z020 FPGA; 95.0% lesser LUT when implementing on XC7Z045 compared to state-of-the-art result. Cryptensor can also flexibly support multiple security levels in NTRU scheme, with no additional hardware. The proposed hardware unifies the computation of two different domains that are critical for IoT applications, which greatly reduces the hardware consumption on edge nodes. </p>

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Section: Evaluation On Polynomial Convolutionmentioning

confidence: 87%

Section: Evaluation On Polynomial Convolutionmentioning

confidence: 87%

Section: Evaluation On Polynomial Convolutionmentioning

confidence: 90%

Section: E Related Workmentioning

confidence: 99%

Section: E Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Cryptensor: A Resource-Shared Co-processor to Accelerate Convolutional Neural Network and Polynomial Convolution

See¹,

Ng²,

Tan³

et al. 2022

Preprint

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Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Srinivas,

Elango

2024

IEEE Access

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To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this convergence poses a significant security challenge, as adversaries can exploit it to extract unauthorized information, compromise system performance, and obtain secret keys. Meanwhile, traditional CMOS features have limitations in addressing hardware vulnerabilities and security threats, so promising post-silicon technologies offer potential solutions. Beyond-CMOS technologies offer avenues to fortify hardware security through distinct physical properties and nontraditional computing paradigms. These advancements bolster authentication processes, enhance key generation mechanisms, ensure hardware integrity and fortify resilience against side-channel attacks, hardware Trojans and quantum-resistant cryptography in securing hardware systems. This article provides a detailed review of hardware security, encompassing the identification and mitigation of threats, the implementation of robust countermeasures, the utilization of innovative primitives, countermeasures, various methodologies and distinct features offered by emerging technologies to resist hardware threats.Moreover, strategies to address challenges, explore future directions, and outline plans for achieving further research outcomes have been put forth in this field.

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A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA

Allam,

Mandal,

Roy

2023

2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)

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Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication

Cited by 7 publications

References 9 publications

Cryptensor: A Resource-Shared Co-processor to Accelerate Convolutional Neural Network and Polynomial Convolution

Cryptensor: A Resource-Shared Co-processor to Accelerate Convolutional Neural Network and Polynomial Convolution

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA

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