Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Park, Byeonggil; Park, Jongsun; Lee, Youngjoo

doi:10.1109/access.2018.2815640

Cited by 9 publications

(12 citation statements)

References 23 publications

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“…As a result, the proposed (106,920, 95,040) block-level interleaved-BCH ECC can recover the burst errors of up to 1080 bits during transmitting a data frame of 106,920 bits. Without applying the block-level interleaving scheme, one can use a long BCH code for correcting total 1080 error bits in a user data of 95,040 bits; however, such a long BCH code requires an impractical amount of hardware complexity due to the increased dimension of finite field [30,31]. It is also possible to apply the RS code as a component code for providing the symbol-level correction [32,33]; however, the RS code only focuses on the burst-error channel condition.…”

Section: Baseband Processing With Block-level Interleaved-bch Codesmentioning

confidence: 99%

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

et al. 2019

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This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

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Section: Baseband Processing With Block-level Interleaved-bch Codesmentioning

confidence: 99%

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

et al. 2019

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“…In noisy channels, using error correction code (ECC) is considered an important for digital communication systems to achieve the reliability of the transmission information [22]. In practical applications, Bose-Chaudhuri-Hocquenghem (BCH) is usually adopted to achieve data reliability among the several ECCs because of its acceptable hardware cost and strong error correcting performance [23]. Furthermore, BCH code outperforms both of turbo and convolutional codes with LTE system in terms of BER performance and lower complexity [17].…”

Section: Introductionmentioning

confidence: 99%

BCH codes for 5G wireless communication systems over multipath fading channel

Hussain

Audah

2020

IJEECS

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<span>Due to its large peak to average power ratio (PAPR) and high out of band emission (OOBE), OFDM doesn't meet the requirements of 5G services. Additionally, it supports only one type of waveform parameters in entire bandwidth. In contrast, f-OFDM is dividing the system's bandwidth into a number of subbands to support several waveform parameters based on various service scenarios. So, Filtered-OFDM (f-OFDM) is considered as a modern enabler of the flexible waveform to overcome the OFDM drawbacks while remaining its advantages as well as, to encounter the new challenges that faced 5G. Nonetheless, there is a trade-off among OOBE, PAPR and SNR performance. Meanwhile, channel coding technology is one of the most important issue in physical layer which is playing an essential role in order to achieve the reliability and latency. So, BCH code has been suggested in this paper for f-OFDM system to achieve the reliability of transmission information and thus improving BER performance over multipath fading channel. Whilst, BCH-LTE system is introduced as a baseline in this paper that using for comparison purpose with proposed system. Simulation results showed that the proposed BCH-f-OFDM system was significantly better than BCH-LTE system in terms of decreasing OOBE and achieving improving in BER performance. Although, PAPR levels was stilling high in proposed system due to the trade-off among OOBE, PAPR and SNR performance. However, the proposed system is considered a promising candidate to meet the requirements of 5G services because of its ability to solve two important issues in between three trade-offs'.</span>

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“…The syndrome generator is the first step of the BCH decoding process [6,20]. The syndromes Si of the received vector r(x) are given as:Si=r(αi)…”

Section: Introductionmentioning

confidence: 99%

“…Second, the solution should be able to scale across different bit errors t . Different configurable BCH decoder solutions have been proposed [20,24], but they lack support for both configurable parameters of the BCH decoders. Inspired by the attempt to solve BCH decoders for multiple GF dimensions in [20], we propose an alternate hybrid approach to have a flexible solution.…”

Section: Introductionmentioning

confidence: 99%

“…Different configurable BCH decoder solutions have been proposed [20,24], but they lack support for both configurable parameters of the BCH decoders. Inspired by the attempt to solve BCH decoders for multiple GF dimensions in [20], we propose an alternate hybrid approach to have a flexible solution. In [20], a hardware solution was proposed to support multiple BCH codes; however, the circuit area increases in order to support multiple GF dimensions because of the dual-mBCH decoders’ requirement.…”

Section: Introductionmentioning

confidence: 99%

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A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs)

Subbiah

Ogunfunmi

2019

Micromachines

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Bose–Chaudhuri–Hocquenghem (BCH) codes are broadly used to correct errors in flash memory systems and digital communications. These codes are cyclic block codes and have their arithmetic fixed over the splitting field of their generator polynomial. There are many solutions proposed using CPUs, hardware, and Graphical Processing Units (GPUs) for the BCH decoders. The performance of these BCH decoders is of ultimate importance for systems involving flash memory. However, it is essential to have a flexible solution to correct multiple bit errors over the different finite fields (GF(2 m )). In this paper, we propose a pragmatic approach to decode BCH codes over the different finite fields using hardware circuits and GPUs in tandem. We propose to employ hardware design for a modified syndrome generator and GPUs for a key-equation solver and an error corrector. Using the above partition, we have shown the ability to support multiple bit errors across different BCH block codes without compromising on the performance. Furthermore, the proposed method to generate modified syndrome has zero latency for scenarios where there are no errors. When there is an error detected, the GPUs are deployed to correct the errors using the iBM and Chien search algorithm. The results have shown that using the modified syndrome approach, we can support different multiple finite fields with high throughput.

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Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Cited by 9 publications

References 23 publications

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

BCH codes for 5G wireless communication systems over multipath fading channel

A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs)

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