Arithmetic Bit-Level Verification Using Network Flow Model

Abstract

Abstract. The paper presents a new approach to functional, bit-level verification of arithmetic circuits. The circuit is modeled as a network of adders and basic Boolean gates, and the computation performed by the circuit is viewed as a flow of binary data through such a network. The verification problem is cast as a Network Flow problem and solved using symbolic term rewriting and simple algebraic techniques. Functional correctness is proved by showing that the symbolic flow computed at the primary inputs is equal to the flow computed at the primary outputs. Experimental results show a potential application of the method to certain classes of arithmetic circuits.

Function Extraction from Arithmetic Bit-Level Circuits

“…Proving this requires solving a separate and difficult Boolean problem. In [1] the same problem is solved by modeling the computation of an arithmetic function as a flow of binary data, and representing it as algebraic expression. The functional correctness is proved by showing equivalence between the input and output signatures.…”

“…In this work we extend the algebraic approach proposed in [1] by modeling the problem as a network flow problem. However, we solve a different problem, namely computing (extracting) a unique arithmetic function implemented by the circuit.…”

“…However, it is possible to detect such a boundary automatically using the signature rewriting scheme adopted by the network-flow approach of [1]. The signals at the boundary between the linear and nonlinear block will be referred to as intermediate inputs, M I, and the corresponding signature as intermediate signature, Sig MI .…”

“…It simply states that weighted sum of the input bits to the module is equal to the weighted sum at its output. As such, the FCL also applies to the entire network [1].…”

“…This can be contributed to the difficulty in modeling wide arithmetic datapaths without resorting to computationally expensive Boolean methods that require bit-blasting, i.e., flattening the design to a bit level netlist. This paper addresses arithmetic verification problem using algebraic approach recently proposed in [1]. It models the circuit as a network of standard arithmetic components, and computation performed by the circuit is viewed as a flow of binary data through the network, represented as a pseudoBoolean expression.…”