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Design ows are the explicit combinations of design transformations, primarily involved in synthesis, placement and routing processes, to accomplish the design of Integrated Circuits (ICs) and System-on-Chip (SoC). Mostly, the ows are developed based on the knowledge of the experts. However, due to the large search space of design ows and the increasing design complexity, developing Intellectual Property (IP)-specic synthesis ows providing high Quality of Result (QoR) is extremely challenging. This work presents a fully autonomous framework that articially produces design-specic synthesis ows without human guidance and baseline ows, using Convolutional Neural Network (CNN). The demonstrations are made by successfully designing logic synthesis ows of three large scaled designs.

The paper presents an algebraic approach to functional verification of gate-level, integer arithmetic circuits. It is based on extracting a unique bit-level polynomial function computed by the circuit directly from its gate-level implementation. The method can be used to verify the arithmetic function computed by the circuit against its known specification, or to extract the arithmetic function implemented by the circuit. Experiments were performed on arithmetic circuits synthesized and mapped onto standard cells using ABC system. The results demonstrate scalability of the method to large arithmetic circuits, such as multipliers, multiply-accumulate, and other elements of arithmetic datapaths with up to 512-bit operands and over 2 Million gates. The procedure has linear runtime and memory complexity, measured by the number of logic gates.

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