Fast Algebraic Rewriting Based on And-Inverter Graphs

Yu, Cunxi; Ciesielski, Maciej; Mishchenko, Alan

doi:10.1109/tcad.2017.2772854

Cited by 46 publications

(28 citation statements)

References 16 publications

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“…In contrast to the algebraic rewriting applied directly to a gate level circuit, as in Figure 1(a), the rewriting employed in our tool operates on the functional AIG representation of the circuit [21]. AIG (And-Inverter Graph) is a combinational Boolean network composed of two-input AND gates and inverters [1].…”

Section: Aig Rewritingmentioning

confidence: 99%

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Rewriting Environment for Arithmetic Circuit Verification

Yasin

et al.

EPiC Series in Computing

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The paper describes a practical software tool for the verification of integer arithmetic circuits. It covers different types of integer multipliers, fused add-multiply circuits, and constant dividers - in general, circuits whose computation can be represented as a polynomial. The verification uses an algebraic model of the circuit and is accomplished by rewriting the polynomial of the binary encoding of the primary outputs (output signature), using the polynomial models of the logic gates, into a polynomial over the primary inputs (input signature). The resulting polynomial represents arithmetic function implemented by the circuit and hence can be used to extract functional specification from its gate-level implementation. The rewriting uses an efficient And-Inverter Graph (AIG) representation to enable extraction of the essential arithmetic components of the circuit. The tool is integrated with the popular ABC system. Its efficiency is illustrated with impressive results for integer multipliers, fused add-multiply circuits, and divide-by-constant circuits. The entire verification system is offered in an open source ABC environment together with an extensive set of benchmarks.

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Section: Aig Rewritingmentioning

confidence: 99%

“…An alternative, and more effective approach to accomplish the verification proof for gatelevel arithmetic circuits is based on algebraic rewriting [20] [21]. It transforms the polynomial at the primary outputs (called the output signature) into a polynomial in terms of primary inputs (the input signature) [20].…”

Section: Introductionmentioning

confidence: 99%

Rewriting Environment for Arithmetic Circuit Verification

Yasin

et al.

EPiC Series in Computing

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“…Currently the most successful automated approach uses polynomial reasoning [4,13,17,18,23] and in recent years has seen significant progress. The approach of [17,18] employs local cancellation of vanishing monomials in converging cones, which allows to verify a large variety of multiplier architectures much more efficiently than previous work.…”

Section: Introductionmentioning

confidence: 99%

“…The approach of [17,18] employs local cancellation of vanishing monomials in converging cones, which allows to verify a large variety of multiplier architectures much more efficiently than previous work. The authors of [4,23] eliminate redundant polynomials by identifying full-and half-adders in the multipliers. This technique is able to verify large simple multipliers, but fails on even slightly more complex multiplier architectures.…”

Section: Introductionmentioning

confidence: 99%

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SAT, Computer Algebra, Multipliers

Kaufmann¹,

Biere²,

Kauers³

EPiC Series in Computing

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Verifying multiplier circuits is an important problem which in practice still requires substantial manual effort. The currently most effective approach uses polynomial reasoning. However parts of a multiplier, i.e., complex final stage adders are hard to verify using computer algebra. In our approach we combine SAT and computer algebra to substantially improve automated verification of integer multipliers. In this paper we focus on the implementation details of our new dedicated reduction engine, which not only allows fully automated adder substitution, but also employs polynomial re- duction efficiently. Our tool is furthermore able to generate proof certificates in the practical algebraic calculus and we also investigate the size of these proofs for one specific multiplier architecture.

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Automated and Scalable Verification of Integer Multipliers

Temel

Slobodová²,

HuntJr.

2020

Lecture Notes in Computer Science

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The automatic formal verification of multiplier designs has been pursued since the introduction of BDDs. We present a new rewriterbased method for efficient and automatic verification of signed and unsigned integer multiplier designs. We have proved the soundness of this method using the ACL2 theorem prover, and we can verify integer multiplier designs with various architectures automatically, including Wallace, Dadda, and 4-to-2 compressor trees, designed with Booth encoding and various types of final stage adders. Our experiments have shown that our approach scales well in terms of time and memory. With our method, we can confirm the correctness of 1024 × 1024-bit multiplier designs within minutes.

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Fast Algebraic Rewriting Based on And-Inverter Graphs

Cited by 46 publications

References 16 publications

Rewriting Environment for Arithmetic Circuit Verification

Rewriting Environment for Arithmetic Circuit Verification

SAT, Computer Algebra, Multipliers

Automated and Scalable Verification of Integer Multipliers

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