Verification of gate-level arithmetic circuits by function extraction

Ciesielski, Maciej; Yu, Cunxi; Brown, W. E.; Liu, Duo; Rossi, André

doi:10.1145/2744769.2744925

Cited by 55 publications

(51 citation statements)

References 22 publications

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“…This section briefly reviews the function extraction technique that motivation our approach. It computes a unique bit-level polynomial function implemented by the circuit directly from its gatelevel implementation [5]. It uses an algebraic model of the circuit, with logic gates represented by the following algebraic expressions, with circuit signals treated as Boolean variables.…”

Section: Function Extraction Using Algebraic Rewritingmentioning

confidence: 99%

Spectral approach to verifying non-linear arithmetic circuits

Yu¹,

Su²,

Yasin³

et al. 2019

Proceedings of the 24th Asia and South Pacific Design Automation Conference

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This paper presents a fast and effective computer algebraic method for analyzing and verifying non-linear integer arithmetic circuits using a novel algebraic spectral model. It introduces a concept of algebraic spectrum, a numerical form of polynomial expression; it uses the distribution of coefficients of the monomials to determine the type of arithmetic function under verification. In contrast to previous works, the proof of functional correctness is achieved by computing an algebraic spectrum combined with local rewriting of word-level polynomials. The speedup is achieved by propagating coefficients through the circuit using And-Inverter Graph (AIG) datastructure. The effectiveness of the method is demonstrated with experiments including standard and Booth multipliers, and other synthesized non-linear arithmetic circuits up to 1024 bits containing over 12 million gates.

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Section: Function Extraction Using Algebraic Rewritingmentioning

confidence: 99%

Spectral approach to verifying non-linear arithmetic circuits

Yu¹,

Su²,

Yasin³

et al. 2019

Proceedings of the 24th Asia and South Pacific Design Automation Conference

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“…Comparing to ADAC, these methods are less scalable, which is demonstrated by the fact that they have been used for approximating multipliers limited to 8-bit operands and adders limited to 16-bit operands only. Apart from that, there are efficient methods for exact equivalence checking based on algebraic computations [8,16]. However, they are so far not known for approximate equivalence checking.…”

Section: Evaluation Related Work and Applicationsmentioning

confidence: 99%

ADAC: Automated Design of Approximate Circuits

Češka

Matyas

Mrázek

et al. 2018

Computer Aided Verification

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Abstract. Approximate circuits with relaxed requirements on functional correctness play an important role in the development of resourceefficient computer systems. Designing approximate circuits is a very complex and time-demanding process trying to find optimal trade-offs between the approximation error and resource savings. In this paper, we present ADAC-a novel framework for automated design of approximate arithmetic circuits. ADAC integrates in a unique way efficient simulation and formal methods for approximate equivalence checking into a search-based circuit optimisation. To make ADAC easily accessible, it is implemented as a module of the ABC tool: a state-of-the-art system for circuit synthesis and verification. Within several hours, ADAC is able to construct high-quality Pareto sets of complex circuits (including even 32-bit multipliers), providing useful trade-offs between the resource consumption and the error that is formally guaranteed. This demonstrates outstanding performance and scalability compared with other existing approaches.

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“…This can be attributed to the difficulty in efficient modeling of arithmetic circuits and datapaths, without resorting to computationally expensive Boolean methods. Contemporary formal techniques, such as Binary Decision Diagrams (BDDs), Boolean Satisfiability (SAT), Satisfiability Modulo Theories (SMT), etc., are not directly applicable to verification of integer and finite field arithmetic circuits [1] [2]. This paper concentrates on formal verification and reverse engineering of finite (Galois) field arithmetic circuits.…”

Section: Introductionmentioning

confidence: 99%

“…The field of size m is constructed using irreducible polynomial P (x), which includes terms of degree C. Yu and M. Ciesielski are with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, 01375. The related tools and benchmarks are released publicly on Github, ycunxi.github.io/Parallel Formal Analysis GaloisField E-mail: ycunxi@umass.edu with d ∈ [0, m] with coefficients in GF (2). The arithmetic operation in the field is then performed modulo P (x).…”

Section: Introductionmentioning

confidence: 99%

“…This information is needed to generate the specification polynomial that describes the circuit functionality regarding its inputs and outputs, necessary for the polynomial reduction process (described in Section II-D). Secondly, these methods are unable to explore parallelism (inherent in GF circuits), as they require that the polynomial division is applied iteratively using reverse-topological order [2] [9] [6]. Thirdly, the approaches applied specifically to GF(2 m ) arithmetic circuits [5] [6], require knowledge of the irreducible polynomial P (x) of the circuit.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

Ciesielski

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Galois field (GF) arithmetic circuits find numerous applications in communications, signal processing, and security engineering. Formal verification techniques of GF circuits are scarce and limited to circuits with known bit positions of the primary inputs and outputs. They also require knowledge of the irreducible polynomial P (x), which affects final hardware implementation. This paper presents a computer algebra technique that performs verification and reverse engineering of GF(2 m ) multipliers directly from the gate-level implementation. The approach is based on extracting a unique irreducible polynomial in a parallel fashion and proceeds in three steps: 1) determine the bit position of the output bits; 2) determine the bit position of the input bits; and 3) extract the irreducible polynomial used in the design. We demonstrate that this method is able to reverse engineer GF(2 m ) multipliers in m threads. Experiments performed on synthesized Mastrovito and Montgomery multipliers with different P (x), including NIST-recommended polynomials, demonstrate high efficiency of the proposed method.

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Verification of gate-level arithmetic circuits by function extraction

Cited by 55 publications

References 22 publications

Spectral approach to verifying non-linear arithmetic circuits

Spectral approach to verifying non-linear arithmetic circuits

ADAC: Automated Design of Approximate Circuits

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

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