ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors

Abstract

In this paper, we introduce an Application-guided Reliability-enhanced Register file Architecture (ARRA) to improve the reliability of RF in embedded processors. ARRA proposes a RF micro-architecture which is guided by binary instrumentation for run-time register mirroring. Our experimental results on an ARRA-enhanced Blackfin processor present that on average the power overhead of ARRA is 70% less than that of a partially-ECC-protected RF, while ARRA reduces RF Vulnerability Factor from 35% to 6.9%, and can correct up to three bit-flips errors. I. INTRODUCTIONThe Register File (RF) has a significant contribution to embedded processors reliability [1] [2]. With the high frequency of accesses to the RF, soft errors in RF rapidly propagate to the data and control path, leading to processor crash or silent data corruption [3]. At the same time, power breakdown of embedded processors reported in [4] shows that the Register File (RF) consumes 15%-36% of overall power of the processor, making RF reliability improvement more challenging. As an example, in Blackfin processor 20% of processor core power (including data and instruction caches) is attributed to the RF itself [5].In recent years, embedded processors are designed with larger register files to reduce the number of references to memory thus increasing performance. Embedded cores such as TI C64x+ [6] and ADI Blackfin [7] have large RFs. Large RFs aid embedded processors to support application variety from control to media applications. We have observed (Section III), that RF utilization considerably changes in different applications and within an application. Many registers are unused in large portions of execution. Therefore, there is a potential for RF reliability improvement by utilizing the passive registers.In this paper, we propose an architecture extension for enhancing RF vulnerability against soft errors, called Application-guided Reliability-enhanced Register file Architecture (ARRA). ARRA relies on the fact that control applications have a high reliability demand while their RF utilization is fairly low. Our proposed ARRA approach is able to correct all single-bit and two-adjacent bit errors, with considerably lower power overhead in comparison to ECC-protected RF. The simulation results on ARRA-extended Blackfin processor show that, for control applications the RF Vulnerability Factor is reduced from %35 to %7 on average with negligible performance overhead. The power overhead in ARRA is %70 less than that in partially-ECC-protected RF.The remainder of this paper is organized as follows. Section II will discuss previous work. Register lifetime analysis

Dynamically adaptive register file architecture for energy reduction in embedded processors

“…Guan and Fei [13] extended this work by eliminating the need to ISA modification and proposed a scheme which considers cross-partition register access of instructions. As opposed to the two mentioned works which used stateretentive low power register [36] consider register lifetime and perform power-gating over individual registers. This scheme operates at function-level granularity, and by analyzing the source code, applies power-gating to the registers that are not used in the execution of each function.…”

A Joint SW/HW Approach for Reducing Register File Vulnerability

“…Tabkhi and Schirner [2012a] illustrated initial binary analysis for the purpose of register mirroring, and Tabkhi and Schirner [2012b] illustrated some ideas about hardware extensions for realizing runtime register mirroring. In this article, we provide a more comprehensive description of the ARRA approach, covering both application and microarchitecture aspects with significantly added details about previous work, approach, and results.…”