This paper introduces a power efficient approach for improving reliability of heterogeneous register files in embedded processors. The approach is based on the fact that control applications have high demands in reliability, while many special-purpose register are unused in a considerable portion of execution. The paper proposes a static application binary analysis which is applied at function-level granularity and offers a systematic way to manage the RF's protection by mirroring the content of used registers into unused ones. The simulation results on an enhanced Blackfin processor demonstrate that Register File Vulnerability Factor (RFVF) is reduced from 35% to 6.9% in cost of 1% performance lost on average for control applications from Mibench suite. I. INTRODUCTIONSoft errors caused by high energy particle strike are exponentially increasing with shrinking feature size, . Register File (RF) as a key component in the processor's performance has also a significant influence over the processor's reliability [1].An investigation on ARM processors shows that more than 50% of errors affecting the correct state of processor comes from faults in the RF [1]. Access frequency to RF is quite high and errors are mostly exposed to the outside. Consequently, an error in RF easily propagates to data path and whole system leading to system crash or silent data corruption [2].At the same time, RF is already one of the main sources of energy dissipation in embedded processors, consuming 15%-36% of the total processor power [3]. ECC (Error Correction Code) or fully duplicated RF may not be applicable to the entire RF due to their huge power overhead. Different RF caching solutions and partial protected RFs have been proposed in order to protect just the most vulnerable register words [4][1]. However, adding ECC or duplication even for part of RF still imposes a considerable amount of static and dynamic power to the processor. For instance, the required energy for an ECC checking is three times higher than a register accesses [5], while it can correct just a single bit flip.In the recent years, processors are designed with larger register files to reduce the number of references to memory thus increasing performance. One trend of embedded processors is composing a complex register file out of heterogeneous register banks with specialized functionality [6]. Heterogeneous RFs aid embedded processors to efficiently support variety of applications from control to media applications. Heterogeneous RFs are currently implemented in embedded processors like ADI Blackfin families [6].

Abstract-Increasing software content in embedded systems and SoCs drives the demand to automatically synthesize software binaries from abstract models. This is especially critical for Hardware dependent Software (HdS) due to the tight coupling.In this paper, we present our approach to automatically synthesize HdS from an abstract system model. We synthesize driver code, interrupt handlers and startup code. We furthermore automatically adjust the application to use RTOS services. We target traditional RTOS-based multi-tasking solutions, as well as a pure interrupt-based implementation (without any RTOS).Our experimental results show the automatic generation of final binary images for six real-life target applications and demonstrate significant productivity gains due to automation. Our HdS synthesis is an enabler for efficient MPSoC development and rapid design space exploration.

Abstract

Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system. Recently, Transaction Level Modeling (TLM) is used to speedup communication simulation at the cost of accuracy.This paper proposes a novel modeling technique called Result Oriented Modeling (ROM) which removes the accuracy drawback of TLM. Using ROM, models yield the same speed as their TLM counterparts, yet still are 100% accurate in timing. ROM utilizes the fact that internal states in the communication channel are not observable by the caller. Hence, ROM omits the internal states entirely and optimistically predicts the end result. Retroactively, the outcome is checked and, if necessary, corrective measures are taken to maintain the accuracy of the model.In this paper, we apply ROM to the AMBA AHB bus architecture. Our experimental results show that ROM exhibits the same high simulation performance as traditional TLM, yet it retains the same accuracy as the bus functional model. Thus, the proposed ROM approach eliminates the speed/accuracy tradeoff exhibited by traditional TLM.

In this paper, we introduce an Application-guided Reliability-enhanced Register file Architecture (ARRA) to improve the reliability of RF in embedded processors. ARRA proposes a RF micro-architecture which is guided by binary instrumentation for run-time register mirroring. Our experimental results on an ARRA-enhanced Blackfin processor present that on average the power overhead of ARRA is 70% less than that of a partially-ECC-protected RF, while ARRA reduces RF Vulnerability Factor from 35% to 6.9%, and can correct up to three bit-flips errors. I. INTRODUCTIONThe Register File (RF) has a significant contribution to embedded processors reliability [1] [2]. With the high frequency of accesses to the RF, soft errors in RF rapidly propagate to the data and control path, leading to processor crash or silent data corruption [3]. At the same time, power breakdown of embedded processors reported in [4] shows that the Register File (RF) consumes 15%-36% of overall power of the processor, making RF reliability improvement more challenging. As an example, in Blackfin processor 20% of processor core power (including data and instruction caches) is attributed to the RF itself [5].In recent years, embedded processors are designed with larger register files to reduce the number of references to memory thus increasing performance. Embedded cores such as TI C64x+ [6] and ADI Blackfin [7] have large RFs. Large RFs aid embedded processors to support application variety from control to media applications. We have observed (Section III), that RF utilization considerably changes in different applications and within an application. Many registers are unused in large portions of execution. Therefore, there is a potential for RF reliability improvement by utilizing the passive registers.In this paper, we propose an architecture extension for enhancing RF vulnerability against soft errors, called Application-guided Reliability-enhanced Register file Architecture (ARRA). ARRA relies on the fact that control applications have a high reliability demand while their RF utilization is fairly low. Our proposed ARRA approach is able to correct all single-bit and two-adjacent bit errors, with considerably lower power overhead in comparison to ECC-protected RF. The simulation results on ARRA-extended Blackfin processor show that, for control applications the RF Vulnerability Factor is reduced from %35 to %7 on average with negligible performance overhead. The power overhead in ARRA is %70 less than that in partially-ECC-protected RF.The remainder of this paper is organized as follows. Section II will discuss previous work. Register lifetime analysis