Application-specific power-efficient approach for reducing register file vulnerability

Tabkhi,; Schirner,

doi:10.1109/date.2012.6176535

Cited by 9 publications

(9 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Functions provide well-known isolation over register accesses in the program code, simplifying tracking register dependencies across different function calls. Further details have been provided in [9].…”

Section: A Register-mirroring Trade-offsmentioning

confidence: 99%

“…In the Blackfin ISA, we chose to extend the the Link/Unlink instructions, as the code size overhead is lower when embedding the MR push and pop operations to the current instructions. Deep analysis has been provided in [9]. Further details of application binary analysis has been provided in [9].…”

Section: Application Analysis and Instrumentationmentioning

confidence: 99%

“…Deep analysis has been provided in [9]. Further details of application binary analysis has been provided in [9].…”

Section: Application Analysis and Instrumentationmentioning

confidence: 99%

“…In contrast, our proposed approach employs a HW/SW integrated extension which improves reliability at significantly lower power consumption than HW-only approaches and outperforms SW-only approaches in improving reliability. ARRA is an extension over [9] which presented aspects of the application binary analysis. In this paper, we cover both application and microarchitecture aspects, also discussing different register mapping alternatives.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors

Tabkhi¹,

Schirner²

2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

View full text Add to dashboard Cite

In this paper, we introduce an Application-guided Reliability-enhanced Register file Architecture (ARRA) to improve the reliability of RF in embedded processors. ARRA proposes a RF micro-architecture which is guided by binary instrumentation for run-time register mirroring. Our experimental results on an ARRA-enhanced Blackfin processor present that on average the power overhead of ARRA is 70% less than that of a partially-ECC-protected RF, while ARRA reduces RF Vulnerability Factor from 35% to 6.9%, and can correct up to three bit-flips errors. I. INTRODUCTIONThe Register File (RF) has a significant contribution to embedded processors reliability [1] [2]. With the high frequency of accesses to the RF, soft errors in RF rapidly propagate to the data and control path, leading to processor crash or silent data corruption [3]. At the same time, power breakdown of embedded processors reported in [4] shows that the Register File (RF) consumes 15%-36% of overall power of the processor, making RF reliability improvement more challenging. As an example, in Blackfin processor 20% of processor core power (including data and instruction caches) is attributed to the RF itself [5].In recent years, embedded processors are designed with larger register files to reduce the number of references to memory thus increasing performance. Embedded cores such as TI C64x+ [6] and ADI Blackfin [7] have large RFs. Large RFs aid embedded processors to support application variety from control to media applications. We have observed (Section III), that RF utilization considerably changes in different applications and within an application. Many registers are unused in large portions of execution. Therefore, there is a potential for RF reliability improvement by utilizing the passive registers.In this paper, we propose an architecture extension for enhancing RF vulnerability against soft errors, called Application-guided Reliability-enhanced Register file Architecture (ARRA). ARRA relies on the fact that control applications have a high reliability demand while their RF utilization is fairly low. Our proposed ARRA approach is able to correct all single-bit and two-adjacent bit errors, with considerably lower power overhead in comparison to ECC-protected RF. The simulation results on ARRA-extended Blackfin processor show that, for control applications the RF Vulnerability Factor is reduced from %35 to %7 on average with negligible performance overhead. The power overhead in ARRA is %70 less than that in partially-ECC-protected RF.The remainder of this paper is organized as follows. Section II will discuss previous work. Register lifetime analysis

show abstract

Section: A Register-mirroring Trade-offsmentioning

confidence: 99%

Section: Application Analysis and Instrumentationmentioning

confidence: 99%

“…Deep analysis has been provided in [9]. Further details of application binary analysis has been provided in [9].…”

Section: Application Analysis and Instrumentationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors

Tabkhi¹,

Schirner²

2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

View full text Add to dashboard Cite

show abstract

“…Tankhi et al determines and analyses an application's RVF for embedded processors using a power e cient approach [51]. Li et al develops a novel methodology and analysis tool to determine the e ect of soft errors on extreme-scale scientific applications [52].…”

Section: Zhang Et Al Analyzes Application Vulnerability For Simultanmentioning

confidence: 99%

ReSense: A Unified Framework for Improving Performance and Reliability in Multicore Architectures

Dey

View full text Add to dashboard Cite

Chip-multiprocessors (CMPs) have become ubiquitous in modern computing and the mainstream architecture for various platforms, including laptops, desktops, and large server machines. As technology scaling continues and more transistors are accommodated on the chip, the number of cores on CMPs is growing, and multi-core machines are scaling up to many-core machines. With this multi-core scaling, two major problems arise: shared-resource contention and soft errors or transient faults. Shared-resource contention can degrade an application's performance significantly, and soft errors increase the probability of incorrect application execution and the production of visible errors. To realize the full potential of multi-and many-core platforms, it is critical to ensure that applications in a workload not only execute e ciently and fast, but also correctly.In this dissertation, we develop a novel, general, and unified framework, ReSense, to address several challenges on multicore architectures including performance optimization, reliability improvement, power and thermal management. The framework includes five components: a general characterization methodology, a characterization metric, a sensitivity score, a thread mapping algorithm, and a run-time system. An instance of the framework is applied in two phases: characterization and mapping. The characterization phase utilizes the general characterization methodology and characterization metric to identify application characteristics without considering any co-runner(s). It generates a resource-sensitivity score for each application in a workload. In the mapping phase, the run-time system uses a thread-mapping algorithm and the sensitivity scores of the applications in a workload to c Abstract d determine the thread-mappings that optimize the objective function of the targeted problem.To demonstrate the utility and e ectiveness of ReSense, we use it to address the problems of shared-resource contention and soft errors for multi-threaded applications. For the resource contention problem, the characterization methodology determines how a multi-threaded application's performance is a ected as it shares a resource in the memory hierarchy. A sensitivity score based on resource contention is produced for each application in a workload.The run-time system uses the resource-contention sensitivity scores and a thread-mapping algorithm to allocate threads from a workload to core to mitigate shared-resource contention, thus improving response time and throughput.For the soft error problem, the characterization methodology determines how a multithreaded application's vulnerability to soft errors in shared caches is a ected by its resource occupancy duration. A sensitivity score based on cache occupancy is produced for each application in a workload. The run-time system uses the cache-occupancy sensitivity scores and a thread-mapping algorithm to allocate workload threads to cores to reduce the occupancy in the shared caches, thus reducing cache vulnerability.Both minimizing...

show abstract

Improving Reliability of Multi-/Many-Core Processors by Using NMR-MPar Approach

Vargas¹,

Ramos²,

Méhaut³

et al. 2019

Radiation Effects on Integrated Circuits and Systems for Space Applications

View full text Add to dashboard Cite

Application-specific power-efficient approach for reducing register file vulnerability

Cited by 9 publications

References 8 publications

ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors

ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors

ReSense: A Unified Framework for Improving Performance and Reliability in Multicore Architectures

Improving Reliability of Multi-/Many-Core Processors by Using NMR-MPar Approach

Contact Info

Product

Resources

About