Array architecture for ATG with 100% fault coverage

El-Ayat, Khaled; Cahn, R.; Chan, Chung Lau; Speers, T.

doi:10.1109/dftvs.1991.199966

Cited by 11 publications

(2 citation statements)

References 4 publications

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“…Testing FPGA's is addressed in the literature such as [4]- [7]. These works and this paper deal with manufacturing test.…”

Section: Introductionmentioning

confidence: 99%

“…Other tests in the field, such as verifying correctly loaded configuration data, are typically handled by architectural features for reprogrammable FPGA's [2]. Reference [4] discusses testing of row-based (segmented channel) FPGA's. The approach sequentially tests every cell using a modified scan procedure, providing 100% fault coverage of single stuck-at faults.…”

Section: Introductionmentioning

confidence: 99%

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Testing configurable LUT-based FPGA's

Huang

Meyer

Chen³

et al. 1998

IEEE Trans. VLSI Syst.

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We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (1-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability). We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

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“…Testing FPGA's is addressed in the literature such as [4]- [7]. These works and this paper deal with manufacturing test.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%