I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays

This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) input/outputs (IOs) of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-bit sum function (1-BSF); the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilising the all zeros' vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4 and Virtex5), the proposed method (with a polynomial time complexity) results in a single test configuration with 100% coverage. These results also show that the proposed method requires a larger number of test vectors and an availability of unused IOs.

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I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays

Zhao¹,

Walker

Lombardi

1998

IEEE Trans. Comput.

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I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays

Cited by 10 publications

References 31 publications

Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT

Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT

Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects

I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays

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